Lines Matching refs:shift
105 val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift; in ti_clk_divider_recalc_rate()
231 val = div_mask(divider) << (divider->shift + 16); in ti_clk_divider_set_rate()
234 val &= ~(div_mask(divider) << divider->shift); in ti_clk_divider_set_rate()
236 val |= value << divider->shift; in ti_clk_divider_set_rate()
251 u8 shift, u8 width, u8 clk_divider_flags, in _register_divider() argument
259 if (width + shift > 16) { in _register_divider()
280 div->shift = shift; in _register_divider()
377 div->shift = setup->bit_shift; in ti_clk_build_component_div()
519 u32 *flags, u8 *div_flags, u8 *width, u8 *shift) in ti_clk_divider_populate() argument
528 *shift = val; in ti_clk_divider_populate()
530 *shift = 0; in ti_clk_divider_populate()
567 u8 shift = 0; in of_ti_divider_clk_setup() local
574 &clk_divider_flags, &width, &shift)) in of_ti_divider_clk_setup()
578 shift, width, clk_divider_flags, table); in of_ti_divider_clk_setup()
601 &div->flags, &div->width, &div->shift) < 0) in of_ti_composite_divider_clk_setup()