771 	struct hw_perf_event *hwc = &event->hw;  in pmu_event_update()  local
775 		prev_raw_count = local64_read(&hwc->prev_count);  in pmu_event_update()
777 	} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,  in pmu_event_update()
794 	struct hw_perf_event *hwc = &event->hw;  in pmu_event_set_period()  local
802 	local64_set(&hwc->prev_count, val);  in pmu_event_set_period()
921 	struct hw_perf_event *hwc = &event->hw;  in cci_pmu_start()  local
922 	int idx = hwc->idx;  in cci_pmu_start()
930 		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));  in cci_pmu_start()
932 	hwc->state = 0;  in cci_pmu_start()
943 		pmu_set_event(cci_pmu, idx, hwc->config_base);  in cci_pmu_start()
954 	struct hw_perf_event *hwc = &event->hw;  in cci_pmu_stop()  local
955 	int idx = hwc->idx;  in cci_pmu_stop()
957 	if (hwc->state & PERF_HES_STOPPED)  in cci_pmu_stop()
971 	hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;  in cci_pmu_stop()
978 	struct hw_perf_event *hwc = &event->hw;  in cci_pmu_add()  local
994 	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;  in cci_pmu_add()
1010 	struct hw_perf_event *hwc = &event->hw;  in cci_pmu_del()  local
1011 	int idx = hwc->idx;  in cci_pmu_del()
1077 	struct hw_perf_event *hwc = &event->hw;  in __hw_perf_event_init()  local
1093 	hwc->idx		= -1;  in __hw_perf_event_init()
1094 	hwc->config_base	= 0;  in __hw_perf_event_init()
1095 	hwc->config		= 0;  in __hw_perf_event_init()
1096 	hwc->event_base		= 0;  in __hw_perf_event_init()
1101 	hwc->config_base	    |= (unsigned long)mapping;  in __hw_perf_event_init()
1108 	hwc->sample_period  = CCI_PMU_CNTR_MASK >> 1;  in __hw_perf_event_init()
1109 	hwc->last_period    = hwc->sample_period;  in __hw_perf_event_init()
1110 	local64_set(&hwc->period_left, hwc->sample_period);  in __hw_perf_event_init()