49 #define roundsm16(x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2, t3, t4, t5, t6, \  argument
56 	vmovdqa .Lpre_tf_lo_s1, t0; \
72 	filter_8bit(x0, t0, t1, t7, t6); \
73 	filter_8bit(x7, t0, t1, t7, t6); \
74 	filter_8bit(x1, t0, t1, t7, t6); \
75 	filter_8bit(x4, t0, t1, t7, t6); \
76 	filter_8bit(x2, t0, t1, t7, t6); \
77 	filter_8bit(x5, t0, t1, t7, t6); \
85 	vmovdqa .Lpost_tf_lo_s1, t0; \
99 	filter_8bit(x0, t0, t1, t7, t6); \
100 	filter_8bit(x7, t0, t1, t7, t6); \
101 	filter_8bit(x3, t0, t1, t7, t6); \
102 	filter_8bit(x6, t0, t1, t7, t6); \
111 	vmovq key, t0; \
117 	vpsrldq $5, t0, t5; \
118 	vpsrldq $1, t0, t1; \
119 	vpsrldq $2, t0, t2; \
120 	vpsrldq $3, t0, t3; \
121 	vpsrldq $4, t0, t4; \
122 	vpshufb t6, t0, t0; \
170 	vpxor t0, x7, x7; \
267 #define rol32_1_16(v0, v1, v2, v3, t0, t1, t2, zero) \  argument
268 	vpcmpgtb v0, zero, t0; \
270 	vpabsb t0, t0; \
280 	vpor t0, v1, v1; \
282 	vpcmpgtb v3, zero, t0; \
284 	vpabsb t0, t0; \
288 	vpor t0, v0, v0;
297 #define fls16(l, l0, l1, l2, l3, l4, l5, l6, l7, r, t0, t1, t2, t3, tt0, \  argument
305 	vmovd kll, t0; \
306 	vpshufb tt0, t0, t3; \
307 	vpsrldq $1, t0, t0; \
308 	vpshufb tt0, t0, t2; \
309 	vpsrldq $1, t0, t0; \
310 	vpshufb tt0, t0, t1; \
311 	vpsrldq $1, t0, t0; \
312 	vpshufb tt0, t0, t0; \
314 	vpand l0, t0, t0; \
319 	rol32_1_16(t3, t2, t1, t0, tt1, tt2, tt3, tt0); \
321 	vpxor l4, t0, l4; \
336 	vmovd krr, t0; \
337 	vpshufb tt0, t0, t3; \
338 	vpsrldq $1, t0, t0; \
339 	vpshufb tt0, t0, t2; \
340 	vpsrldq $1, t0, t0; \
341 	vpshufb tt0, t0, t1; \
342 	vpsrldq $1, t0, t0; \
343 	vpshufb tt0, t0, t0; \
345 	vpor 4 * 16(r), t0, t0; \
350 	vpxor 0 * 16(r), t0, t0; \
354 	vmovdqu t0, 0 * 16(r); \
364 	vmovd krl, t0; \
365 	vpshufb tt0, t0, t3; \
366 	vpsrldq $1, t0, t0; \
367 	vpshufb tt0, t0, t2; \
368 	vpsrldq $1, t0, t0; \
369 	vpshufb tt0, t0, t1; \
370 	vpsrldq $1, t0, t0; \
371 	vpshufb tt0, t0, t0; \
373 	vpand 0 * 16(r), t0, t0; \
378 	rol32_1_16(t3, t2, t1, t0, tt1, tt2, tt3, tt0); \
380 	vpxor 4 * 16(r), t0, t0; \
384 	vmovdqu t0, 4 * 16(r); \
395 	vmovd klr, t0; \
396 	vpshufb tt0, t0, t3; \
397 	vpsrldq $1, t0, t0; \
398 	vpshufb tt0, t0, t2; \
399 	vpsrldq $1, t0, t0; \
400 	vpshufb tt0, t0, t1; \
401 	vpsrldq $1, t0, t0; \
402 	vpshufb tt0, t0, t0; \
404 	vpor l4, t0, t0; \
409 	vpxor l0, t0, l0; \