Lines Matching refs:Op2
444 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
447 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
450 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \
453 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
477 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
480 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
483 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
489 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
492 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
510 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
513 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
516 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
519 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
522 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
525 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
528 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
531 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
535 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
538 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
541 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
545 { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
549 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
552 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
555 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
558 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
561 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
564 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
568 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
571 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
574 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
577 { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
580 { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
584 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
587 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
591 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
594 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
598 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
602 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101),
605 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
609 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
612 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
616 { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
620 { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
624 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
627 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
630 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
633 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
636 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
639 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
642 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
645 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
648 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
651 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
654 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
657 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
660 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
664 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
667 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
671 { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
674 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
677 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
750 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
752 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
754 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
756 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
759 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
768 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
770 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
774 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
777 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
779 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
782 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
784 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
789 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
791 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
794 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
806 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
810 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
813 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
817 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
820 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
834 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
837 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
839 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
841 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
843 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
845 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
847 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
865 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
867 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
868 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
869 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
870 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
871 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
872 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
873 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
874 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
875 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
876 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
877 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
882 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
883 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
884 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
887 { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
888 { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
889 { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
890 { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
891 { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
892 { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
893 { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
894 { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
895 { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
896 { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
897 { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
898 { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
899 { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
901 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
902 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
903 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
904 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
907 { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
909 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
913 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
914 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
915 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
961 if (params->Op2 != r->Op2) in find_reg()
1067 params.Op2 = 0; in kvm_handle_cp_64()
1119 params.Op2 = (hsr >> 17) & 0x7; in kvm_handle_cp_32()
1235 params.Op2 = (esr >> 17) & 0x7; in kvm_handle_sys_reg()
1271 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) in index_to_params()
1347 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1349 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1351 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1353 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1355 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1357 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1359 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1361 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1363 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1365 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1367 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1369 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1371 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1373 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1375 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1377 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1379 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1381 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1383 { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1599 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); in sys_reg_to_index()