Lines Matching refs:r0
44 mov r0, sp
73 @ The abort handler must return the aborted address in r0, and
97 THUMB( stmia sp, {r0 - r12} )
131 ldmia r0, {r4 - r6}
132 add r0, sp, #S_PC @ here for interlock avoidance
134 str r4, [sp] @ save preserved r0
135 stmia r0, {r5 - r7} @ lr_<exception>,
138 mov r0, sp
154 UNWIND(.save {r0 - pc} )
157 SPFIX( str r0, [sp] ) @ temporarily saved
158 SPFIX( mov r0, sp )
159 SPFIX( tst r0, #4 ) @ test original stack alignment
160 SPFIX( ldr r0, [sp] ) @ restored
167 ldmia r0, {r3 - r5}
172 str r3, [sp, #-4]! @ save the "real" r0 copied
188 uaccess_save r0
190 uaccess_disable r0
218 ldr r0, [tsk, #TI_FLAGS] @ get flags
220 movne r0, #0 @ force flags to 0
221 tst r0, #_TIF_NEED_RESCHED
235 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
236 tst r0, #_TIF_NEED_RESCHED
248 ldr r2, [r0, #S_PC]
250 str r2, [r0, #S_PC]
269 @ r0 - instruction
272 ldr r0, [r4, #-4]
275 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
276 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
281 orr r0, r9, r0, lsl #16
289 mov r0, sp @ struct pt_regs *regs
310 mov r0, sp @ struct pt_regs *regs
340 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
341 THUMB( msr cpsr_c, r0 )
345 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
346 THUMB( msr cpsr_c, r0 )
349 add r0, sp, #8 @ struct pt_regs *regs
354 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
355 THUMB( msr cpsr_c, r0 )
359 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
360 THUMB( msr cpsr_c, r0 )
532 3: ldrht r0, [r2]
533 ARM_BE8(rev16 r0, r0) @ little endian instruction
1025 * of which is copied into r0 for the mode specific abort handler.
1036 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1039 stmia sp, {r0, lr} @ save r0, lr
1046 mrs r0, cpsr
1047 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1048 msr spsr_cxsf, r0
1054 THUMB( adr r0, 1f )
1055 THUMB( ldr lr, [r0, lr, lsl #2] )
1056 mov r0, sp