Lines Matching refs:cmu
56 clocks = <&cmu CLK_ARM_CLK>;
191 cmu: clock-controller@10030000 { label
192 compatible = "samsung,exynos3250-cmu";
195 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
196 <&cmu CLK_MOUT_ACLK_266_SUB>;
197 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
198 <&cmu CLK_FIN_PLL>;
202 compatible = "samsung,exynos3250-cmu-dmc";
219 clocks = <&cmu CLK_TMU_APBIF>;
241 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
266 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
269 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
271 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
281 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
291 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
307 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
319 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
328 clocks = <&cmu CLK_USBOTG>;
339 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
351 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
363 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
379 clocks = <&cmu CLK_PDMA0>;
390 clocks = <&cmu CLK_PDMA1>;
404 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
416 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
427 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
436 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
447 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
460 clocks = <&cmu CLK_I2C0>;
473 clocks = <&cmu CLK_I2C1>;
486 clocks = <&cmu CLK_I2C2>;
499 clocks = <&cmu CLK_I2C3>;
512 clocks = <&cmu CLK_I2C4>;
525 clocks = <&cmu CLK_I2C5>;
538 clocks = <&cmu CLK_I2C6>;
551 clocks = <&cmu CLK_I2C7>;
566 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
582 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
594 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
638 clocks = <&cmu CLK_PPMURIGHT>;
646 clocks = <&cmu CLK_PPMULEFT>;
654 clocks = <&cmu CLK_PPMUCAMIF>;
662 clocks = <&cmu CLK_PPMULCD0>;
670 clocks = <&cmu CLK_PPMUFILE>;
678 clocks = <&cmu CLK_PPMUG3D>;
686 clocks = <&cmu CLK_PPMUMFC_L>;