76 	iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);  in axs10x_enable_gpio_intc_wire()
77 	iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);  in axs10x_enable_gpio_intc_wire()
78 	iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);  in axs10x_enable_gpio_intc_wire()
79 	iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);  in axs10x_enable_gpio_intc_wire()
83 write_cgu_reg(uint32_t value, void __iomem *reg, void __iomem *lock_reg)  in write_cgu_reg()
111 	board.val = ioread32((void __iomem *)creg);  in axs10x_print_board_ver()
122 	if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))  in axs10x_early_init()
253 axs101_set_memmap(void __iomem *base, const struct aperture map[16])  in axs101_set_memmap()
282 	axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap);  in axs101_early_init()
283 	iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);  in axs101_early_init()
286 	axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN,  in axs101_early_init()
288 	iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);  in axs101_early_init()
292 		axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4),  in axs101_early_init()
295 	iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */  in axs101_early_init()
298 	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);  in axs101_early_init()
301 	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);  in axs101_early_init()
304 	iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);  in axs101_early_init()
307 	iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);  in axs101_early_init()
342 	idiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 0);  in axs103_get_freq()
343 	fbdiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 4);  in axs103_get_freq()
344 	odiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 8);  in axs103_get_freq()
378 		      (void __iomem *)AXC003_CGU + 0x80 + 0,  in axs103_set_freq()
379 		      (void __iomem *)AXC003_CGU + 0x110);  in axs103_set_freq()
382 		      (void __iomem *)AXC003_CGU + 0x80 + 4,  in axs103_set_freq()
383 		      (void __iomem *)AXC003_CGU + 0x110);  in axs103_set_freq()
386 		      (void __iomem *)AXC003_CGU + 0x80 + 8,  in axs103_set_freq()
387 		      (void __iomem *)AXC003_CGU + 0x110);  in axs103_set_freq()
443 	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);  in axs103_early_init()
446 		  (void __iomem *) CREG_CPU_TUN_IO_CTRL);  in axs103_early_init()
449 	iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX  in axs103_early_init()
453 	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);  in axs103_early_init()