Lines Matching refs:clock

21 - compatible: Should contain a chip-specific clock block compatible
22 	string and (if applicable) may contain a chassis-version clock
35 	Chassis-version clock strings include:
40 	represents the clock register set
51 - clock-frequency: Input system clock frequency (SYSCLK)
52 - clocks: If clock-frequency is not specified, sysclk may be provided
53 	as an input clock.  Either clock-frequency or clocks must be
58 The clockgen node should act as a clock provider, though in older device
59 trees the children of the clockgen node are the clock providers.
61 When the clockgen node is a clock provider, #clock-cells = <2>.
62 The first cell of the clock specifier is the clock type, and the
63 second cell is the clock index for the specified type.
76 		clock-frequency = <133333333>;
78 		#clock-cells = <2>;
92 Most of the bindings are from the common clock binding[1].
93  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
101 	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
102 		It takes parent's clock-frequency as its clock.
103 	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
104 		It takes parent's clock-frequency as its clock.
105 	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
106 	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
107 - #clock-cells: From common clock binding. The number of cells in a
108 	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
111 	clock-specifier cell may take the following values:
117 - clocks: Should be the phandle of input parent clock
118 - clock-names: From common clock binding, indicates the clock name
119 - clock-output-names: From common clock binding, indicates the names of
121 - reg: Should be the offset and length of clock block base address.
129 		clock-frequency = <133333333>;
135 			#clock-cells = <0>;
137 			clock-output-names = "sysclk";
141 			#clock-cells = <1>;
145 			clock-output-names = "pll0", "pll0-div2";
149 			#clock-cells = <1>;
153 			clock-output-names = "pll1", "pll1-div2";
157 			#clock-cells = <0>;
161 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
162 			clock-output-names = "cmux0";
166 			#clock-cells = <0>;
170 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
171 			clock-output-names = "cmux1";
175 			#clock-cells = <1>;
179 			clock-output-names = "platform-pll", "platform-pll-div2";
184 Example for legacy clock consumer: