Lines Matching refs:dev_dbg
106 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); in dwc2_init_fs_ls_pclk_sel()
188 dev_dbg(hsotg->dev, "FS PHY selected\n"); in dwc2_fs_phy_init()
211 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); in dwc2_fs_phy_init()
249 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); in dwc2_hs_phy_init()
257 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); in dwc2_hs_phy_init()
301 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); in dwc2_phy_init()
326 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); in dwc2_gahbcfg_init()
336 dev_dbg(hsotg->dev, "Slave Only Mode\n"); in dwc2_gahbcfg_init()
340 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n", in dwc2_gahbcfg_init()
346 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); in dwc2_gahbcfg_init()
348 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); in dwc2_gahbcfg_init()
350 dev_dbg(hsotg->dev, "Using Slave mode\n"); in dwc2_gahbcfg_init()
410 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); in dwc2_core_init()
456 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); in dwc2_core_init()
469 dev_dbg(hsotg->dev, "Host Mode\n"); in dwc2_core_init()
472 dev_dbg(hsotg->dev, "Device Mode\n"); in dwc2_core_init()
488 dev_dbg(hsotg->dev, "%s()\n", __func__); in dwc2_enable_host_interrupts()
596 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); in dwc2_config_fifos()
601 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", readl(hsotg->regs + GRXFSIZ)); in dwc2_config_fifos()
604 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", in dwc2_config_fifos()
611 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", in dwc2_config_fifos()
615 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", in dwc2_config_fifos()
623 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", in dwc2_config_fifos()
657 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); in dwc2_core_host_init()
740 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", in dwc2_core_host_init()
756 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); in dwc2_core_host_init()
760 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", in dwc2_core_host_init()
1117 dev_dbg(hsotg->dev, "desc DMA enabled\n"); in dwc2_hc_halt()
1807 dev_dbg(hsotg->dev, "Host Global Registers\n"); in dwc2_dump_host_registers()
1809 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1812 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1815 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1818 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1821 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1824 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1828 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1833 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1837 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); in dwc2_dump_host_registers()
1839 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1842 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1845 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1848 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1851 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1854 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1858 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
1878 dev_dbg(hsotg->dev, "Core Global Registers\n"); in dwc2_dump_global_registers()
1880 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1883 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1886 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1889 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1892 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1895 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1898 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1901 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1904 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1907 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1910 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1913 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1916 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1919 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1922 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1925 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1928 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1931 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1934 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1937 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1940 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1943 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1946 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1949 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
1953 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2070 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); in dwc2_set_param_otg_cap()
2091 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val); in dwc2_set_param_dma_enable()
2114 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); in dwc2_set_param_dma_desc_enable()
2131 dev_dbg(hsotg->dev, in dwc2_set_param_host_support_fs_ls_low_power()
2153 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); in dwc2_set_param_enable_dynamic_fifo()
2172 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); in dwc2_set_param_host_rx_fifo_size()
2191 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", in dwc2_set_param_host_nperio_tx_fifo_size()
2211 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", in dwc2_set_param_host_perio_tx_fifo_size()
2231 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); in dwc2_set_param_max_transfer_size()
2250 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); in dwc2_set_param_max_packet_count()
2269 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); in dwc2_set_param_host_channels()
2317 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); in dwc2_set_param_phy_type()
2351 dev_dbg(hsotg->dev, "Setting speed to %d\n", val); in dwc2_set_param_speed()
2384 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", in dwc2_set_param_host_ls_low_power_phy_clk()
2399 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); in dwc2_set_param_phy_ulpi_ddr()
2415 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); in dwc2_set_param_phy_ulpi_ext_vbus()
2445 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); in dwc2_set_param_phy_utmi_width()
2459 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); in dwc2_set_param_ulpi_fs_ls()
2473 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); in dwc2_set_param_ts_dline()
2501 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); in dwc2_set_param_i2c_enable()
2530 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); in dwc2_set_param_en_multiple_tx_fifo()
2558 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); in dwc2_set_param_reload_ctl()
2583 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); in dwc2_set_param_otg_ver()
2599 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); in dwc2_set_param_uframe_sched()
2612 dev_dbg(hsotg->dev, "%s()\n", __func__); in dwc2_set_parameters()
2677 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", in dwc2_get_hwparams()
2687 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); in dwc2_get_hwparams()
2688 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); in dwc2_get_hwparams()
2689 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); in dwc2_get_hwparams()
2690 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); in dwc2_get_hwparams()
2691 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); in dwc2_get_hwparams()
2701 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); in dwc2_get_hwparams()
2702 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); in dwc2_get_hwparams()
2767 dev_dbg(hsotg->dev, "Detected values from hardware:\n"); in dwc2_get_hwparams()
2768 dev_dbg(hsotg->dev, " op_mode=%d\n", in dwc2_get_hwparams()
2770 dev_dbg(hsotg->dev, " arch=%d\n", in dwc2_get_hwparams()
2772 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", in dwc2_get_hwparams()
2774 dev_dbg(hsotg->dev, " power_optimized=%d\n", in dwc2_get_hwparams()
2776 dev_dbg(hsotg->dev, " i2c_enable=%d\n", in dwc2_get_hwparams()
2778 dev_dbg(hsotg->dev, " hs_phy_type=%d\n", in dwc2_get_hwparams()
2780 dev_dbg(hsotg->dev, " fs_phy_type=%d\n", in dwc2_get_hwparams()
2782 dev_dbg(hsotg->dev, " utmi_phy_data_wdith=%d\n", in dwc2_get_hwparams()
2784 dev_dbg(hsotg->dev, " num_dev_ep=%d\n", in dwc2_get_hwparams()
2786 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", in dwc2_get_hwparams()
2788 dev_dbg(hsotg->dev, " host_channels=%d\n", in dwc2_get_hwparams()
2790 dev_dbg(hsotg->dev, " max_transfer_size=%d\n", in dwc2_get_hwparams()
2792 dev_dbg(hsotg->dev, " max_packet_count=%d\n", in dwc2_get_hwparams()
2794 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", in dwc2_get_hwparams()
2796 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", in dwc2_get_hwparams()
2798 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", in dwc2_get_hwparams()
2800 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", in dwc2_get_hwparams()
2802 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", in dwc2_get_hwparams()
2804 dev_dbg(hsotg->dev, " total_fifo_size=%d\n", in dwc2_get_hwparams()
2806 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n", in dwc2_get_hwparams()
2808 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", in dwc2_get_hwparams()
2810 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", in dwc2_get_hwparams()
2812 dev_dbg(hsotg->dev, "\n"); in dwc2_get_hwparams()