78 	if (hsotg->core_params->dma_enable <= 0)  in dwc2_enable_common_interrupts()
97 	     hsotg->core_params->ulpi_fs_ls > 0) ||  in dwc2_init_fs_ls_pclk_sel()
98 	    hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {  in dwc2_init_fs_ls_pclk_sel()
210 	if (hsotg->core_params->i2c_enable > 0) {  in dwc2_fs_phy_init()
246 	switch (hsotg->core_params->phy_type) {  in dwc2_hs_phy_init()
252 		if (hsotg->core_params->phy_ulpi_ddr > 0)  in dwc2_hs_phy_init()
259 		if (hsotg->core_params->phy_utmi_width == 16)  in dwc2_hs_phy_init()
285 	if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&  in dwc2_phy_init()
286 	    hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {  in dwc2_phy_init()
300 	    hsotg->core_params->ulpi_fs_ls > 0) {  in dwc2_phy_init()
327 		if (hsotg->core_params->ahbcfg != -1) {  in dwc2_gahbcfg_init()
329 			ahbcfg |= hsotg->core_params->ahbcfg &  in dwc2_gahbcfg_init()
341 		hsotg->core_params->dma_enable,  in dwc2_gahbcfg_init()
342 		hsotg->core_params->dma_desc_enable);  in dwc2_gahbcfg_init()
344 	if (hsotg->core_params->dma_enable > 0) {  in dwc2_gahbcfg_init()
345 		if (hsotg->core_params->dma_desc_enable > 0)  in dwc2_gahbcfg_init()
351 		hsotg->core_params->dma_desc_enable = 0;  in dwc2_gahbcfg_init()
354 	if (hsotg->core_params->dma_enable > 0)  in dwc2_gahbcfg_init()
371 		if (hsotg->core_params->otg_cap ==  in dwc2_gusbcfg_init()
374 		if (hsotg->core_params->otg_cap !=  in dwc2_gusbcfg_init()
382 		if (hsotg->core_params->otg_cap !=  in dwc2_gusbcfg_init()
416 	if (hsotg->core_params->phy_ulpi_ext_vbus ==  in dwc2_core_init()
422 	if (hsotg->core_params->ts_dline > 0)  in dwc2_core_init()
453 	if (hsotg->core_params->otg_ver > 0)  in dwc2_core_init()
456 	dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);  in dwc2_core_init()
527 	struct dwc2_core_params *params = hsotg->core_params;  in dwc2_calculate_dynamic_fifo()
586 	struct dwc2_core_params *params = hsotg->core_params;  in dwc2_config_fifos()
626 	if (hsotg->core_params->en_multiple_tx_fifo > 0 &&  in dwc2_config_fifos()
664 	if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {  in dwc2_core_host_init()
675 	if (hsotg->core_params->reload_ctl > 0) {  in dwc2_core_host_init()
681 	if (hsotg->core_params->dma_desc_enable > 0) {  in dwc2_core_host_init()
692 			hsotg->core_params->dma_desc_enable = 0;  in dwc2_core_host_init()
718 	if (hsotg->core_params->dma_desc_enable <= 0) {  in dwc2_core_host_init()
723 		num_channels = hsotg->core_params->host_channels;  in dwc2_core_host_init()
858 	if (hsotg->core_params->dma_desc_enable <= 0) {  in dwc2_hc_enable_dma_ints()
891 	if (hsotg->core_params->dma_enable > 0) {  in dwc2_hc_enable_ints()
1111 	if (hsotg->core_params->dma_desc_enable <= 0) {  in dwc2_hc_halt()
1121 	if (hsotg->core_params->dma_enable <= 0) {  in dwc2_hc_halt()
1337 	u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size;  in dwc2_hc_start_transfer()
1338 	u16 max_hc_pkt_count = hsotg->core_params->max_packet_count;  in dwc2_hc_start_transfer()
1347 		if (hsotg->core_params->dma_enable <= 0) {  in dwc2_hc_start_transfer()
1464 	if (hsotg->core_params->dma_enable > 0) {  in dwc2_hc_start_transfer()
1516 	if (hsotg->core_params->dma_enable <= 0 &&  in dwc2_hc_start_transfer()
1826 	if (hsotg->core_params->dma_desc_enable > 0) {  in dwc2_dump_host_registers()
1836 	for (i = 0; i < hsotg->core_params->host_channels; i++) {  in dwc2_dump_host_registers()
1856 		if (hsotg->core_params->dma_desc_enable > 0) {  in dwc2_dump_host_registers()
2073 	hsotg->core_params->otg_cap = val;  in dwc2_set_param_otg_cap()
2094 	hsotg->core_params->dma_enable = val;  in dwc2_set_param_dma_enable()
2101 	if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||  in dwc2_set_param_dma_desc_enable()
2112 		val = (hsotg->core_params->dma_enable > 0 &&  in dwc2_set_param_dma_desc_enable()
2117 	hsotg->core_params->dma_desc_enable = val;  in dwc2_set_param_dma_desc_enable()
2135 	hsotg->core_params->host_support_fs_ls_low_power = val;  in dwc2_set_param_host_support_fs_ls_low_power()
2156 	hsotg->core_params->enable_dynamic_fifo = val;  in dwc2_set_param_enable_dynamic_fifo()
2175 	hsotg->core_params->host_rx_fifo_size = val;  in dwc2_set_param_host_rx_fifo_size()
2195 	hsotg->core_params->host_nperio_tx_fifo_size = val;  in dwc2_set_param_host_nperio_tx_fifo_size()
2215 	hsotg->core_params->host_perio_tx_fifo_size = val;  in dwc2_set_param_host_perio_tx_fifo_size()
2234 	hsotg->core_params->max_transfer_size = val;  in dwc2_set_param_max_transfer_size()
2253 	hsotg->core_params->max_packet_count = val;  in dwc2_set_param_max_packet_count()
2272 	hsotg->core_params->host_channels = val;  in dwc2_set_param_host_channels()
2320 	hsotg->core_params->phy_type = val;  in dwc2_set_param_phy_type()
2325 	return hsotg->core_params->phy_type;  in dwc2_get_param_phy_type()
2354 	hsotg->core_params->speed = val;  in dwc2_set_param_speed()
2388 	hsotg->core_params->host_ls_low_power_phy_clk = val;  in dwc2_set_param_host_ls_low_power_phy_clk()
2402 	hsotg->core_params->phy_ulpi_ddr = val;  in dwc2_set_param_phy_ulpi_ddr()
2418 	hsotg->core_params->phy_ulpi_ext_vbus = val;  in dwc2_set_param_phy_ulpi_ext_vbus()
2448 	hsotg->core_params->phy_utmi_width = val;  in dwc2_set_param_phy_utmi_width()
2462 	hsotg->core_params->ulpi_fs_ls = val;  in dwc2_set_param_ulpi_fs_ls()
2476 	hsotg->core_params->ts_dline = val;  in dwc2_set_param_ts_dline()
2504 	hsotg->core_params->i2c_enable = val;  in dwc2_set_param_i2c_enable()
2533 	hsotg->core_params->en_multiple_tx_fifo = val;  in dwc2_set_param_en_multiple_tx_fifo()
2561 	hsotg->core_params->reload_ctl = val;  in dwc2_set_param_reload_ctl()
2567 		hsotg->core_params->ahbcfg = val;  in dwc2_set_param_ahbcfg()
2569 		hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<  in dwc2_set_param_ahbcfg()
2586 	hsotg->core_params->otg_ver = val;  in dwc2_set_param_otg_ver()
2602 	hsotg->core_params->uframe_sched = val;  in dwc2_set_param_uframe_sched()
2819 	return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103;  in dwc2_get_otg_version()