Lines Matching refs:BIT4
385 #define MASK_OVERRUN BIT4
423 #define IRQ_RI BIT4
2233 if (status & (BIT5 + BIT4)) { in isr_rdma()
2258 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4171 case 6: val |= BIT4; break; in async_mode()
4173 case 8: val |= BIT5 + BIT4; break; in async_mode()
4211 case 6: val |= BIT4; break; in async_mode()
4213 case 8: val |= BIT5 + BIT4; break; in async_mode()
4337 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; in sync_mode()
4338 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
4436 val |= BIT4; /* 100, rxclk = DPLL */ in sync_mode()
4509 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; in tx_set_idle()
4514 tcr &= ~(BIT5 + BIT4); in tx_set_idle()
4587 val |= BIT4; in msc_set_vcr()