Lines Matching refs:pxa2xx_spi_read
119 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; in pxa2xx_spi_txfifo_full()
303 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) in pxa2xx_spi_flush()
304 pxa2xx_spi_read(drv_data, SSDR); in pxa2xx_spi_flush()
305 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); in pxa2xx_spi_flush()
329 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) in null_reader()
331 pxa2xx_spi_read(drv_data, SSDR); in null_reader()
352 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) in u8_reader()
354 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u8_reader()
375 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) in u16_reader()
377 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u16_reader()
398 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) in u32_reader()
400 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u32_reader()
479 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; in reset_sccr1()
494 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); in int_error_stop()
527 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? in interrupt_transfer()
530 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; in interrupt_transfer()
562 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); in interrupt_transfer()
617 status = pxa2xx_spi_read(drv_data, SSSR); in ssp_int()
621 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); in ssp_int()
637 pxa2xx_spi_read(drv_data, SSCR0) in ssp_int()
640 pxa2xx_spi_read(drv_data, SSCR1) in ssp_int()
969 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) in pump_transfers()
973 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) in pump_transfers()
980 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) in pump_transfers()
984 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) in pump_transfers()
985 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) in pump_transfers()
1035 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); in pxa2xx_spi_unprepare_transfer()