70 				struct seq_file *s, unsigned offset)  in sirfsoc_pin_dbg_show()  argument
205 	struct pinctrl_gpio_range *range, unsigned offset)  in sirfsoc_pinmux_request_gpio()  argument
217 	muxval = muxval | (1 << (offset - range->pin_base));  in sirfsoc_pinmux_request_gpio()
408 sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)  in sirfsoc_gpio_to_bank()  argument
410 	return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];  in sirfsoc_gpio_to_bank()
413 static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)  in sirfsoc_gpio_to_bankoff()  argument
415 	return offset % SIRFSOC_GPIO_BANK_SIZE;  in sirfsoc_gpio_to_bankoff()
424 	u32 val, offset;  in sirfsoc_gpio_irq_ack()  local
427 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);  in sirfsoc_gpio_irq_ack()
431 	val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_ack()
433 	writel(val, sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_ack()
442 	u32 val, offset;  in __sirfsoc_gpio_irq_mask()  local
445 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);  in __sirfsoc_gpio_irq_mask()
449 	val = readl(sgpio->chip.regs + offset);  in __sirfsoc_gpio_irq_mask()
452 	writel(val, sgpio->chip.regs + offset);  in __sirfsoc_gpio_irq_mask()
472 	u32 val, offset;  in sirfsoc_gpio_irq_unmask()  local
475 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);  in sirfsoc_gpio_irq_unmask()
479 	val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_unmask()
482 	writel(val, sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_unmask()
493 	u32 val, offset;  in sirfsoc_gpio_irq_type()  local
496 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);  in sirfsoc_gpio_irq_type()
500 	val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_type()
533 	writel(val, sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_type()
607 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)  in sirfsoc_gpio_request()  argument
610 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);  in sirfsoc_gpio_request()
613 	if (pinctrl_request_gpio(chip->base + offset))  in sirfsoc_gpio_request()
622 	sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));  in sirfsoc_gpio_request()
623 	__sirfsoc_gpio_irq_mask(sgpio, bank, offset);  in sirfsoc_gpio_request()
630 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)  in sirfsoc_gpio_free()  argument
633 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);  in sirfsoc_gpio_free()
638 	__sirfsoc_gpio_irq_mask(sgpio, bank, offset);  in sirfsoc_gpio_free()
639 	sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));  in sirfsoc_gpio_free()
643 	pinctrl_free_gpio(chip->base + offset);  in sirfsoc_gpio_free()
652 	unsigned offset;  in sirfsoc_gpio_direction_input()  local
654 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);  in sirfsoc_gpio_direction_input()
658 	sirfsoc_gpio_set_input(sgpio, offset);  in sirfsoc_gpio_direction_input()
667 					   unsigned offset,  in sirfsoc_gpio_set_output()  argument
675 	out_ctrl = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_set_output()
683 	writel(out_ctrl, sgpio->chip.regs + offset);  in sirfsoc_gpio_set_output()
694 	u32 offset;  in sirfsoc_gpio_direction_output()  local
697 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);  in sirfsoc_gpio_direction_output()
701 	sirfsoc_gpio_set_output(sgpio, bank, offset, value);  in sirfsoc_gpio_direction_output()
708 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)  in sirfsoc_gpio_get_value()  argument
711 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);  in sirfsoc_gpio_get_value()
717 	val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));  in sirfsoc_gpio_get_value()
724 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,  in sirfsoc_gpio_set_value()  argument
728 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);  in sirfsoc_gpio_set_value()
734 	ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));  in sirfsoc_gpio_set_value()
739 	writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));  in sirfsoc_gpio_set_value()
752 			u32 offset = SIRFSOC_GPIO_CTRL(i, n);  in sirfsoc_gpio_set_pullup()  local
753 			u32 val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_set_pullup()
756 			writel(val, sgpio->chip.regs + offset);  in sirfsoc_gpio_set_pullup()
769 			u32 offset = SIRFSOC_GPIO_CTRL(i, n);  in sirfsoc_gpio_set_pulldown()  local
770 			u32 val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_set_pulldown()
773 			writel(val, sgpio->chip.regs + offset);  in sirfsoc_gpio_set_pulldown()