527 	struct pci_dev *bridge = bus->self;  in pci_setup_cardbus()  local
531 	dev_info(&bridge->dev, "CardBus bridge to %pR\n",  in pci_setup_cardbus()
535 	pcibios_resource_to_bus(bridge->bus, &region, res);  in pci_setup_cardbus()
541 		dev_info(&bridge->dev, "  bridge window %pR\n", res);  in pci_setup_cardbus()
542 		pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,  in pci_setup_cardbus()
544 		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,  in pci_setup_cardbus()
549 	pcibios_resource_to_bus(bridge->bus, &region, res);  in pci_setup_cardbus()
551 		dev_info(&bridge->dev, "  bridge window %pR\n", res);  in pci_setup_cardbus()
552 		pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,  in pci_setup_cardbus()
554 		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,  in pci_setup_cardbus()
559 	pcibios_resource_to_bus(bridge->bus, &region, res);  in pci_setup_cardbus()
561 		dev_info(&bridge->dev, "  bridge window %pR\n", res);  in pci_setup_cardbus()
562 		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,  in pci_setup_cardbus()
564 		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,  in pci_setup_cardbus()
569 	pcibios_resource_to_bus(bridge->bus, &region, res);  in pci_setup_cardbus()
571 		dev_info(&bridge->dev, "  bridge window %pR\n", res);  in pci_setup_cardbus()
572 		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,  in pci_setup_cardbus()
574 		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,  in pci_setup_cardbus()
591 static void pci_setup_bridge_io(struct pci_dev *bridge)  in pci_setup_bridge_io()  argument
601 	if (bridge->io_window_1k)  in pci_setup_bridge_io()
605 	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];  in pci_setup_bridge_io()
606 	pcibios_resource_to_bus(bridge->bus, &region, res);  in pci_setup_bridge_io()
608 		pci_read_config_word(bridge, PCI_IO_BASE, &l);  in pci_setup_bridge_io()
614 		dev_info(&bridge->dev, "  bridge window %pR\n", res);  in pci_setup_bridge_io()
621 	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);  in pci_setup_bridge_io()
623 	pci_write_config_word(bridge, PCI_IO_BASE, l);  in pci_setup_bridge_io()
625 	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);  in pci_setup_bridge_io()
628 static void pci_setup_bridge_mmio(struct pci_dev *bridge)  in pci_setup_bridge_mmio()  argument
635 	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];  in pci_setup_bridge_mmio()
636 	pcibios_resource_to_bus(bridge->bus, &region, res);  in pci_setup_bridge_mmio()
640 		dev_info(&bridge->dev, "  bridge window %pR\n", res);  in pci_setup_bridge_mmio()
644 	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);  in pci_setup_bridge_mmio()
647 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)  in pci_setup_bridge_mmio_pref()  argument
656 	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);  in pci_setup_bridge_mmio_pref()
660 	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];  in pci_setup_bridge_mmio_pref()
661 	pcibios_resource_to_bus(bridge->bus, &region, res);  in pci_setup_bridge_mmio_pref()
669 		dev_info(&bridge->dev, "  bridge window %pR\n", res);  in pci_setup_bridge_mmio_pref()
673 	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);  in pci_setup_bridge_mmio_pref()
676 	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);  in pci_setup_bridge_mmio_pref()
677 	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);  in pci_setup_bridge_mmio_pref()
682 	struct pci_dev *bridge = bus->self;  in __pci_setup_bridge()  local
684 	dev_info(&bridge->dev, "PCI bridge to %pR\n",  in __pci_setup_bridge()
688 		pci_setup_bridge_io(bridge);  in __pci_setup_bridge()
691 		pci_setup_bridge_mmio(bridge);  in __pci_setup_bridge()
694 		pci_setup_bridge_mmio_pref(bridge);  in __pci_setup_bridge()
696 	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);  in __pci_setup_bridge()
708 int pci_claim_bridge_resource(struct pci_dev *bridge, int i)  in pci_claim_bridge_resource()  argument
713 	if (pci_claim_resource(bridge, i) == 0)  in pci_claim_bridge_resource()
716 	if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)  in pci_claim_bridge_resource()
719 	if (!pci_bus_clip_resource(bridge, i))  in pci_claim_bridge_resource()
724 		pci_setup_bridge_io(bridge);  in pci_claim_bridge_resource()
727 		pci_setup_bridge_mmio(bridge);  in pci_claim_bridge_resource()
730 		pci_setup_bridge_mmio_pref(bridge);  in pci_claim_bridge_resource()
736 	if (pci_claim_resource(bridge, i) == 0)  in pci_claim_bridge_resource()
749 	struct pci_dev *bridge = bus->self;  in pci_bridge_check_ranges()  local
752 	b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];  in pci_bridge_check_ranges()
755 	pci_read_config_word(bridge, PCI_IO_BASE, &io);  in pci_bridge_check_ranges()
757 		pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);  in pci_bridge_check_ranges()
758 		pci_read_config_word(bridge, PCI_IO_BASE, &io);  in pci_bridge_check_ranges()
759 		pci_write_config_word(bridge, PCI_IO_BASE, 0x0);  in pci_bridge_check_ranges()
767 	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)  in pci_bridge_check_ranges()
770 	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);  in pci_bridge_check_ranges()
772 		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,  in pci_bridge_check_ranges()
774 		pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);  in pci_bridge_check_ranges()
775 		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);  in pci_bridge_check_ranges()
789 		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,  in pci_bridge_check_ranges()
791 		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,  in pci_bridge_check_ranges()
793 		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);  in pci_bridge_check_ranges()
796 		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,  in pci_bridge_check_ranges()
1129 	struct pci_dev *bridge = bus->self;  in pci_bus_size_cardbus()  local
1130 	struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];  in pci_bus_size_cardbus()
1145 		add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,  in pci_bus_size_cardbus()
1157 		add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,  in pci_bus_size_cardbus()
1163 	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);  in pci_bus_size_cardbus()
1166 		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);  in pci_bus_size_cardbus()
1167 		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);  in pci_bus_size_cardbus()
1174 	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);  in pci_bus_size_cardbus()
1177 		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);  in pci_bus_size_cardbus()
1178 		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);  in pci_bus_size_cardbus()
1195 			add_to_list(realloc_head, bridge, b_res+2,  in pci_bus_size_cardbus()
1211 		add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,  in pci_bus_size_cardbus()
1383 static void __pci_bridge_assign_resources(const struct pci_dev *bridge,  in __pci_bridge_assign_resources()  argument
1389 	pdev_assign_resources_sorted((struct pci_dev *)bridge,  in __pci_bridge_assign_resources()
1392 	b = bridge->subordinate;  in __pci_bridge_assign_resources()
1398 	switch (bridge->class >> 8) {  in __pci_bridge_assign_resources()
1408 		dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n",  in __pci_bridge_assign_resources()
1743 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)  in pci_assign_unassigned_bridge_resources()  argument
1745 	struct pci_bus *parent = bridge->subordinate;  in pci_assign_unassigned_bridge_resources()
1757 	__pci_bridge_assign_resources(bridge, &add_list, &fail_head);  in pci_assign_unassigned_bridge_resources()
1797 	retval = pci_reenable_device(bridge);  in pci_assign_unassigned_bridge_resources()
1799 		dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval);  in pci_assign_unassigned_bridge_resources()
1800 	pci_set_master(bridge);  in pci_assign_unassigned_bridge_resources()