605 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);  in pci_raw_set_power_state()
1002 	pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);  in pci_restore_pcix_state()
1231 			pci_write_config_word(dev, PCI_COMMAND,  in do_pci_enable_device()
1512 		pci_write_config_word(dev, PCI_COMMAND, pci_command);  in do_pci_disable_device()
1620 	pci_write_config_word(dev, pmcsr_pos, pmcsr);  in pci_check_pme_status()
1720 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);  in pci_pme_active()
2291 	pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);  in pci_std_enable_acs()
2783 		pci_write_config_word(dev, PCI_COMMAND, cmd);  in __pci_set_master()
2913 		pci_write_config_word(dev, PCI_COMMAND, cmd);  in pci_set_mwi()
2953 		pci_write_config_word(dev, PCI_COMMAND, cmd);  in pci_clear_mwi()
2980 		pci_write_config_word(pdev, PCI_COMMAND, new);  in pci_intx()
3009 	pci_write_config_word(dev, PCI_COMMAND,  in pci_intx_mask_supported()
3023 		pci_write_config_word(dev, PCI_COMMAND, orig);  in pci_intx_mask_supported()
3126 		pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);  in pci_msi_off()
3132 		pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);  in pci_msi_off()
3248 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);  in pci_pm_reset()
3253 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);  in pci_pm_reset()
3265 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);  in pci_reset_secondary_bus()
3273 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);  in pci_reset_secondary_bus()
3445 	pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);  in pci_dev_save_and_disable()
4059 		if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))  in pcix_set_mmrbc()
4295 		pci_write_config_word(dev, PCI_COMMAND, cmd);  in pci_set_vga_state()
4311 			pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,  in pci_set_vga_state()
4428 	pci_write_config_word(dev, PCI_COMMAND, command);  in pci_reassigndev_resource_alignment()