Lines Matching refs:PWR_BASEADDR_MAC
68 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
71 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
74 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
77 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
85 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
97 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
99 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},
106 PWR_BASEADDR_MAC, PWR_CMD_WRITE, \
111 PWR_BASEADDR_MAC, \
116 PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, \
140 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
149 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
152 PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
177 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
181 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
188 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
191 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
198 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
206 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
209 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
213 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
217 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
221 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
225 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
229 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
232 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
235 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
238 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
241 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
245 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
255 PWR_INTF_USB_MSK, PWR_BASEADDR_MAC,\
258 PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
261 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
265 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
269 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
273 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
277 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
281 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
285 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
288 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\