Lines Matching refs:rt2x00_set_field32
98 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); in rt2800_bbp_write()
99 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_write()
100 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_write()
101 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); in rt2800_bbp_write()
102 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_write()
127 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_read()
128 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_read()
129 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); in rt2800_bbp_read()
130 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_read()
155 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); in rt2800_rfcsr_write()
156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); in rt2800_rfcsr_write()
157 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); in rt2800_rfcsr_write()
158 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); in rt2800_rfcsr_write()
183 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); in rt2800_rfcsr_read()
184 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); in rt2800_rfcsr_read()
185 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); in rt2800_rfcsr_read()
210 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); in rt2800_rf_write()
211 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); in rt2800_rf_write()
212 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); in rt2800_rf_write()
213 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); in rt2800_rf_write()
379 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); in rt2800_enable_wlan_rt3290()
380 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); in rt2800_enable_wlan_rt3290()
381 rt2x00_set_field32(®, WLAN_CLK_EN, 0); in rt2800_enable_wlan_rt3290()
382 rt2x00_set_field32(®, WLAN_EN, 1); in rt2800_enable_wlan_rt3290()
417 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); in rt2800_enable_wlan_rt3290()
418 rt2x00_set_field32(®, WLAN_CLK_EN, 1); in rt2800_enable_wlan_rt3290()
419 rt2x00_set_field32(®, WLAN_RESET, 1); in rt2800_enable_wlan_rt3290()
422 rt2x00_set_field32(®, WLAN_RESET, 0); in rt2800_enable_wlan_rt3290()
450 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); in rt2800_mcu_request()
451 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); in rt2800_mcu_request()
452 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); in rt2800_mcu_request()
453 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); in rt2800_mcu_request()
457 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); in rt2800_mcu_request()
510 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); in rt2800_disable_wpdma()
511 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); in rt2800_disable_wpdma()
512 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); in rt2800_disable_wpdma()
513 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); in rt2800_disable_wpdma()
514 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); in rt2800_disable_wpdma()
659 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); in rt2800_load_firmware()
660 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); in rt2800_load_firmware()
720 rt2x00_set_field32(&word, TXWI_W0_FRAG, in rt2800_write_tx_data()
722 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, in rt2800_write_tx_data()
724 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); in rt2800_write_tx_data()
725 rt2x00_set_field32(&word, TXWI_W0_TS, in rt2800_write_tx_data()
727 rt2x00_set_field32(&word, TXWI_W0_AMPDU, in rt2800_write_tx_data()
729 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, in rt2800_write_tx_data()
731 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); in rt2800_write_tx_data()
732 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); in rt2800_write_tx_data()
733 rt2x00_set_field32(&word, TXWI_W0_BW, in rt2800_write_tx_data()
735 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, in rt2800_write_tx_data()
737 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); in rt2800_write_tx_data()
738 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); in rt2800_write_tx_data()
742 rt2x00_set_field32(&word, TXWI_W1_ACK, in rt2800_write_tx_data()
744 rt2x00_set_field32(&word, TXWI_W1_NSEQ, in rt2800_write_tx_data()
746 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); in rt2800_write_tx_data()
747 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, in rt2800_write_tx_data()
750 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, in rt2800_write_tx_data()
752 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); in rt2800_write_tx_data()
753 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); in rt2800_write_tx_data()
979 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, in rt2800_update_beacons_setup()
999 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_write_beacon()
1089 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_clear_beacon()
1191 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); in rt2800_brightness_set()
1195 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, in rt2800_brightness_set()
1198 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, in rt2800_brightness_set()
1201 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, in rt2800_brightness_set()
1278 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); in rt2800_config_wcid_attr_bssidx()
1279 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, in rt2800_config_wcid_attr_bssidx()
1296 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, in rt2800_config_wcid_attr_cipher()
1303 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, in rt2800_config_wcid_attr_cipher()
1305 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, in rt2800_config_wcid_attr_cipher()
1307 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); in rt2800_config_wcid_attr_cipher()
1312 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); in rt2800_config_wcid_attr_cipher()
1313 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); in rt2800_config_wcid_attr_cipher()
1314 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); in rt2800_config_wcid_attr_cipher()
1315 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); in rt2800_config_wcid_attr_cipher()
1368 rt2x00_set_field32(®, field, in rt2800_config_shared_key()
1512 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, in rt2800_config_filter()
1514 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, in rt2800_config_filter()
1516 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, in rt2800_config_filter()
1518 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); in rt2800_config_filter()
1519 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); in rt2800_config_filter()
1520 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, in rt2800_config_filter()
1522 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); in rt2800_config_filter()
1523 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); in rt2800_config_filter()
1524 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, in rt2800_config_filter()
1526 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, in rt2800_config_filter()
1528 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, in rt2800_config_filter()
1530 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, in rt2800_config_filter()
1532 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, in rt2800_config_filter()
1534 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, in rt2800_config_filter()
1536 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); in rt2800_config_filter()
1537 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, in rt2800_config_filter()
1539 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, in rt2800_config_filter()
1556 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); in rt2800_config_intf()
1564 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); in rt2800_config_intf()
1565 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); in rt2800_config_intf()
1566 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); in rt2800_config_intf()
1567 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); in rt2800_config_intf()
1571 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); in rt2800_config_intf()
1572 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); in rt2800_config_intf()
1573 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); in rt2800_config_intf()
1574 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); in rt2800_config_intf()
1592 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); in rt2800_config_intf()
1603 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); in rt2800_config_intf()
1604 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); in rt2800_config_intf()
1690 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); in rt2800_config_ht_opmode()
1691 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); in rt2800_config_ht_opmode()
1695 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); in rt2800_config_ht_opmode()
1696 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); in rt2800_config_ht_opmode()
1700 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); in rt2800_config_ht_opmode()
1701 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); in rt2800_config_ht_opmode()
1705 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); in rt2800_config_ht_opmode()
1706 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); in rt2800_config_ht_opmode()
1717 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, in rt2800_config_erp()
1719 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, in rt2800_config_erp()
1726 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, in rt2800_config_erp()
1739 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, in rt2800_config_erp()
1744 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); in rt2800_config_erp()
1750 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800_config_erp()
1768 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); in rt2800_config_3572bt_ant()
1769 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); in rt2800_config_3572bt_ant()
1771 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); in rt2800_config_3572bt_ant()
1772 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); in rt2800_config_3572bt_ant()
1784 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); in rt2800_config_3572bt_ant()
1785 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); in rt2800_config_3572bt_ant()
1803 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); in rt2800_set_ant_diversity()
1810 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); in rt2800_set_ant_diversity()
1811 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); in rt2800_set_ant_diversity()
1972 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); in rt2800_config_channel_rf2xxx()
1975 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); in rt2800_config_channel_rf2xxx()
1978 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); in rt2800_config_channel_rf2xxx()
1979 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); in rt2800_config_channel_rf2xxx()
1981 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); in rt2800_config_channel_rf2xxx()
1990 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, in rt2800_config_channel_rf2xxx()
1996 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); in rt2800_config_channel_rf2xxx()
1998 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, in rt2800_config_channel_rf2xxx()
2004 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); in rt2800_config_channel_rf2xxx()
2006 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); in rt2800_config_channel_rf2xxx()
2007 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); in rt2800_config_channel_rf2xxx()
2010 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); in rt2800_config_channel_rf2xxx()
2266 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); in rt2800_config_channel_rf3052()
2268 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); in rt2800_config_channel_rf3052()
2270 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); in rt2800_config_channel_rf3052()
2770 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, in rt2800_config_channel_rf55xx()
3289 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); in rt2800_config_channel()
3290 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); in rt2800_config_channel()
3291 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); in rt2800_config_channel()
3302 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, in rt2800_config_channel()
3304 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, in rt2800_config_channel()
3309 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, in rt2800_config_channel()
3311 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, in rt2800_config_channel()
3316 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, in rt2800_config_channel()
3319 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); in rt2800_config_channel()
3321 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, in rt2800_config_channel()
3329 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); in rt2800_config_channel()
3330 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); in rt2800_config_channel()
3334 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); in rt2800_config_channel()
3335 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); in rt2800_config_channel()
3339 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); in rt2800_config_channel()
3340 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); in rt2800_config_channel()
3344 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); in rt2800_config_channel()
3345 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); in rt2800_config_channel()
3368 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); in rt2800_config_channel()
3370 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); in rt2800_config_channel()
3372 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); in rt2800_config_channel()
3380 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); in rt2800_config_channel()
3381 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); in rt2800_config_channel()
3383 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); in rt2800_config_channel()
3384 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); in rt2800_config_channel()
3387 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); in rt2800_config_channel()
3388 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); in rt2800_config_channel()
3739 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
3741 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
3743 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
3750 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
3752 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
3754 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
3761 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
3763 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
3765 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
3772 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
3774 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
3776 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
3787 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
3789 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
3791 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
3798 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
3800 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
3802 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
3809 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
3811 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
3813 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
3824 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
3826 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
3828 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
3835 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
3837 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
3839 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
3846 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
3848 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
3850 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
3857 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
3859 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
3861 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
3872 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
3874 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
3876 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
3883 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
3885 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
3887 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
3894 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
3896 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
3898 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
3905 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
3907 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
3909 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
3920 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
3922 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
3924 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
3931 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
3933 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
3935 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
3942 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
3944 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
3946 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
3953 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
3955 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
3957 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
3968 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
3970 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
3972 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
3979 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
3981 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
3983 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
3990 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
3992 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
3994 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
4005 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4007 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4009 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
4016 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4018 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4020 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
4027 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); in rt2800_config_txpower_rt3593()
4028 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); in rt2800_config_txpower_rt3593()
4029 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, in rt2800_config_txpower_rt3593()
4036 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); in rt2800_config_txpower_rt3593()
4037 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); in rt2800_config_txpower_rt3593()
4038 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, in rt2800_config_txpower_rt3593()
4049 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], in rt2800_config_txpower_rt3593()
4051 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], in rt2800_config_txpower_rt3593()
4053 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], in rt2800_config_txpower_rt3593()
4189 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); in rt2800_config_txpower_rt28xx()
4200 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); in rt2800_config_txpower_rt28xx()
4211 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); in rt2800_config_txpower_rt28xx()
4222 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); in rt2800_config_txpower_rt28xx()
4238 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); in rt2800_config_txpower_rt28xx()
4249 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); in rt2800_config_txpower_rt28xx()
4260 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); in rt2800_config_txpower_rt28xx()
4271 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); in rt2800_config_txpower_rt28xx()
4348 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); in rt2800_vco_calibration()
4351 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); in rt2800_vco_calibration()
4355 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); in rt2800_vco_calibration()
4361 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); in rt2800_vco_calibration()
4364 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); in rt2800_vco_calibration()
4368 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); in rt2800_vco_calibration()
4383 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, in rt2800_config_retry_limit()
4385 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, in rt2800_config_retry_limit()
4402 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); in rt2800_config_ps()
4403 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, in rt2800_config_ps()
4405 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); in rt2800_config_ps()
4411 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); in rt2800_config_ps()
4412 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); in rt2800_config_ps()
4413 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); in rt2800_config_ps()
4581 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); in rt2800_init_registers()
4582 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); in rt2800_init_registers()
4583 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); in rt2800_init_registers()
4584 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); in rt2800_init_registers()
4585 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_init_registers()
4586 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); in rt2800_init_registers()
4592 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); in rt2800_init_registers()
4593 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); in rt2800_init_registers()
4599 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); in rt2800_init_registers()
4605 rt2x00_set_field32(®, LDO0_EN, 1); in rt2800_init_registers()
4606 rt2x00_set_field32(®, LDO_BGSEL, 3); in rt2800_init_registers()
4611 rt2x00_set_field32(®, OSC_ROSC_EN, 1); in rt2800_init_registers()
4612 rt2x00_set_field32(®, OSC_CAL_REQ, 1); in rt2800_init_registers()
4613 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); in rt2800_init_registers()
4617 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); in rt2800_init_registers()
4621 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); in rt2800_init_registers()
4622 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); in rt2800_init_registers()
4623 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); in rt2800_init_registers()
4624 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); in rt2800_init_registers()
4628 rt2x00_set_field32(®, PLL_CONTROL, 1); in rt2800_init_registers()
4709 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); in rt2800_init_registers()
4710 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); in rt2800_init_registers()
4711 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); in rt2800_init_registers()
4712 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); in rt2800_init_registers()
4713 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); in rt2800_init_registers()
4714 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); in rt2800_init_registers()
4715 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); in rt2800_init_registers()
4716 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); in rt2800_init_registers()
4720 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); in rt2800_init_registers()
4721 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); in rt2800_init_registers()
4722 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); in rt2800_init_registers()
4726 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); in rt2800_init_registers()
4730 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); in rt2800_init_registers()
4732 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); in rt2800_init_registers()
4733 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0); in rt2800_init_registers()
4734 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0); in rt2800_init_registers()
4738 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); in rt2800_init_registers()
4739 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); in rt2800_init_registers()
4740 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); in rt2800_init_registers()
4741 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); in rt2800_init_registers()
4742 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); in rt2800_init_registers()
4743 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); in rt2800_init_registers()
4744 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); in rt2800_init_registers()
4750 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15); in rt2800_init_registers()
4751 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31); in rt2800_init_registers()
4752 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); in rt2800_init_registers()
4753 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); in rt2800_init_registers()
4754 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); in rt2800_init_registers()
4755 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); in rt2800_init_registers()
4759 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); in rt2800_init_registers()
4760 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); in rt2800_init_registers()
4761 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0); in rt2800_init_registers()
4762 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); in rt2800_init_registers()
4763 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1); in rt2800_init_registers()
4764 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); in rt2800_init_registers()
4765 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); in rt2800_init_registers()
4769 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); in rt2800_init_registers()
4770 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4771 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4772 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4773 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4774 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4775 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
4776 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4777 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
4778 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); in rt2800_init_registers()
4782 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); in rt2800_init_registers()
4783 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4784 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4785 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4786 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4787 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4788 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
4789 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4790 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
4791 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); in rt2800_init_registers()
4795 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); in rt2800_init_registers()
4796 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4797 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4798 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4799 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4800 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4801 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
4802 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4803 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
4804 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
4808 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); in rt2800_init_registers()
4809 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4810 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4811 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4812 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4813 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4814 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); in rt2800_init_registers()
4815 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4816 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); in rt2800_init_registers()
4817 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
4821 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); in rt2800_init_registers()
4822 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4823 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4824 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4825 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4826 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4827 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
4828 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4829 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
4830 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
4834 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); in rt2800_init_registers()
4835 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4836 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4837 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4838 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4839 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4840 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); in rt2800_init_registers()
4841 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4842 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); in rt2800_init_registers()
4843 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
4850 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); in rt2800_init_registers()
4851 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); in rt2800_init_registers()
4852 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); in rt2800_init_registers()
4853 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); in rt2800_init_registers()
4854 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); in rt2800_init_registers()
4855 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); in rt2800_init_registers()
4856 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); in rt2800_init_registers()
4857 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); in rt2800_init_registers()
4858 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); in rt2800_init_registers()
4867 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); in rt2800_init_registers()
4868 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); in rt2800_init_registers()
4869 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); in rt2800_init_registers()
4870 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); in rt2800_init_registers()
4871 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); in rt2800_init_registers()
4872 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); in rt2800_init_registers()
4873 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); in rt2800_init_registers()
4874 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); in rt2800_init_registers()
4875 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); in rt2800_init_registers()
4876 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); in rt2800_init_registers()
4883 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); in rt2800_init_registers()
4884 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, in rt2800_init_registers()
4886 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0); in rt2800_init_registers()
4899 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); in rt2800_init_registers()
4900 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); in rt2800_init_registers()
4901 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); in rt2800_init_registers()
4902 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); in rt2800_init_registers()
4903 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); in rt2800_init_registers()
4929 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); in rt2800_init_registers()
4933 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); in rt2800_init_registers()
4938 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); in rt2800_init_registers()
4939 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); in rt2800_init_registers()
4940 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); in rt2800_init_registers()
4941 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); in rt2800_init_registers()
4942 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); in rt2800_init_registers()
4943 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); in rt2800_init_registers()
4944 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); in rt2800_init_registers()
4945 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); in rt2800_init_registers()
4949 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); in rt2800_init_registers()
4950 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); in rt2800_init_registers()
4951 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); in rt2800_init_registers()
4952 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); in rt2800_init_registers()
4953 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); in rt2800_init_registers()
4954 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); in rt2800_init_registers()
4955 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); in rt2800_init_registers()
4956 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); in rt2800_init_registers()
4960 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); in rt2800_init_registers()
4961 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); in rt2800_init_registers()
4962 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); in rt2800_init_registers()
4963 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); in rt2800_init_registers()
4964 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); in rt2800_init_registers()
4965 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); in rt2800_init_registers()
4966 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); in rt2800_init_registers()
4967 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); in rt2800_init_registers()
4971 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); in rt2800_init_registers()
4972 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); in rt2800_init_registers()
4973 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); in rt2800_init_registers()
4974 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); in rt2800_init_registers()
4981 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); in rt2800_init_registers()
4982 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); in rt2800_init_registers()
5001 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); in rt2800_init_registers()
5008 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); in rt2800_init_registers()
5009 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); in rt2800_init_registers()
5010 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); in rt2800_init_registers()
5011 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); in rt2800_init_registers()
5012 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); in rt2800_init_registers()
5560 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); in rt2800_init_bbp_53xx()
5561 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); in rt2800_init_bbp_53xx()
5562 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); in rt2800_init_bbp_53xx()
5563 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); in rt2800_init_bbp_53xx()
5565 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); in rt2800_init_bbp_53xx()
5567 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); in rt2800_init_bbp_53xx()
5724 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); in rt2800_led_open_drain_enable()
6057 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_30xx()
6058 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_30xx()
6069 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_30xx()
6075 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_30xx()
6077 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_30xx()
6082 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); in rt2800_init_rfcsr_30xx()
6271 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); in rt2800_init_rfcsr_3390()
6327 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_3572()
6328 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3572()
6332 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_3572()
6333 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3572()
6396 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); in rt2800_init_rfcsr_3593()
6397 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); in rt2800_init_rfcsr_3593()
6447 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_3593()
6448 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3593()
6452 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_3593()
6773 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); in rt2800_enable_radio()
6774 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800_enable_radio()
6780 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); in rt2800_enable_radio()
6781 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); in rt2800_enable_radio()
6782 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); in rt2800_enable_radio()
6783 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); in rt2800_enable_radio()
6787 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); in rt2800_enable_radio()
6788 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); in rt2800_enable_radio()
6820 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); in rt2800_disable_radio()
6821 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800_disable_radio()
6866 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); in rt2800_efuse_read()
6867 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); in rt2800_efuse_read()
6868 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); in rt2800_efuse_read()
7773 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); in rt2800_probe_hw()
7844 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); in rt2800_set_rts_threshold()
7848 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7852 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7856 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7860 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7864 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7868 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7911 rt2x00_set_field32(®, field, queue->txop); in rt2800_conf_tx()
7919 rt2x00_set_field32(®, field, queue->aifs); in rt2800_conf_tx()
7923 rt2x00_set_field32(®, field, queue->cw_min); in rt2800_conf_tx()
7927 rt2x00_set_field32(®, field, queue->cw_max); in rt2800_conf_tx()
7934 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); in rt2800_conf_tx()
7935 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); in rt2800_conf_tx()
7936 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); in rt2800_conf_tx()
7937 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); in rt2800_conf_tx()