Lines Matching refs:trans
90 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) in iwl_pcie_free_fw_monitor() argument
92 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_free_fw_monitor()
97 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, in iwl_pcie_free_fw_monitor()
106 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans) in iwl_pcie_alloc_fw_monitor() argument
108 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_alloc_fw_monitor()
115 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, in iwl_pcie_alloc_fw_monitor()
132 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, in iwl_pcie_alloc_fw_monitor()
134 if (dma_mapping_error(trans->dev, phys)) { in iwl_pcie_alloc_fw_monitor()
139 IWL_INFO(trans, in iwl_pcie_alloc_fw_monitor()
153 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) in iwl_trans_pcie_read_shr() argument
155 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, in iwl_trans_pcie_read_shr()
157 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); in iwl_trans_pcie_read_shr()
160 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) in iwl_trans_pcie_write_shr() argument
162 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); in iwl_trans_pcie_write_shr()
163 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, in iwl_trans_pcie_write_shr()
167 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) in iwl_pcie_set_pwr() argument
169 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) in iwl_pcie_set_pwr()
170 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, in iwl_pcie_set_pwr()
174 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, in iwl_pcie_set_pwr()
182 static void iwl_pcie_apm_config(struct iwl_trans *trans) in iwl_pcie_apm_config() argument
184 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_apm_config()
198 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); in iwl_pcie_apm_config()
200 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); in iwl_pcie_apm_config()
201 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); in iwl_pcie_apm_config()
204 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; in iwl_pcie_apm_config()
205 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", in iwl_pcie_apm_config()
207 trans->ltr_enabled ? "En" : "Dis"); in iwl_pcie_apm_config()
215 static int iwl_pcie_apm_init(struct iwl_trans *trans) in iwl_pcie_apm_init() argument
218 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); in iwl_pcie_apm_init()
226 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) in iwl_pcie_apm_init()
227 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, in iwl_pcie_apm_init()
234 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, in iwl_pcie_apm_init()
238 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); in iwl_pcie_apm_init()
244 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_init()
247 iwl_pcie_apm_config(trans); in iwl_pcie_apm_init()
250 if (trans->cfg->base_params->pll_cfg_val) in iwl_pcie_apm_init()
251 iwl_set_bit(trans, CSR_ANA_PLL_CFG, in iwl_pcie_apm_init()
252 trans->cfg->base_params->pll_cfg_val); in iwl_pcie_apm_init()
258 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_apm_init()
265 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_init()
269 IWL_DEBUG_INFO(trans, "Failed to init the card\n"); in iwl_pcie_apm_init()
273 if (trans->cfg->host_interrupt_operation_mode) { in iwl_pcie_apm_init()
288 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
289 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
290 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); in iwl_pcie_apm_init()
291 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
292 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
302 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) { in iwl_pcie_apm_init()
303 iwl_write_prph(trans, APMG_CLK_EN_REG, in iwl_pcie_apm_init()
308 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_init()
312 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, in iwl_pcie_apm_init()
316 set_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_init()
329 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) in iwl_pcie_apm_lp_xtal_enable() argument
337 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
341 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in iwl_pcie_apm_lp_xtal_enable()
349 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_apm_lp_xtal_enable()
355 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
360 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); in iwl_pcie_apm_lp_xtal_enable()
362 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
371 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_lp_xtal_enable()
378 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, in iwl_pcie_apm_lp_xtal_enable()
380 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
388 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in iwl_pcie_apm_lp_xtal_enable()
393 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); in iwl_pcie_apm_lp_xtal_enable()
394 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | in iwl_pcie_apm_lp_xtal_enable()
399 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); in iwl_pcie_apm_lp_xtal_enable()
400 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & in iwl_pcie_apm_lp_xtal_enable()
407 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_lp_xtal_enable()
414 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
418 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
422 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
427 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
432 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) in iwl_pcie_apm_stop_master() argument
437 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); in iwl_pcie_apm_stop_master()
439 ret = iwl_poll_bit(trans, CSR_RESET, in iwl_pcie_apm_stop_master()
443 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); in iwl_pcie_apm_stop_master()
445 IWL_DEBUG_INFO(trans, "stop master\n"); in iwl_pcie_apm_stop_master()
450 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) in iwl_pcie_apm_stop() argument
452 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); in iwl_pcie_apm_stop()
455 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_apm_stop()
456 iwl_pcie_apm_init(trans); in iwl_pcie_apm_stop()
459 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) in iwl_pcie_apm_stop()
460 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_stop()
462 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { in iwl_pcie_apm_stop()
463 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_apm_stop()
465 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_stop()
469 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_apm_stop()
475 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_stop()
478 iwl_pcie_apm_stop_master(trans); in iwl_pcie_apm_stop()
480 if (trans->cfg->lp_xtal_workaround) { in iwl_pcie_apm_stop()
481 iwl_pcie_apm_lp_xtal_enable(trans); in iwl_pcie_apm_stop()
486 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in iwl_pcie_apm_stop()
494 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_stop()
498 static int iwl_pcie_nic_init(struct iwl_trans *trans) in iwl_pcie_nic_init() argument
500 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_nic_init()
504 iwl_pcie_apm_init(trans); in iwl_pcie_nic_init()
508 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) in iwl_pcie_nic_init()
509 iwl_pcie_set_pwr(trans, false); in iwl_pcie_nic_init()
511 iwl_op_mode_nic_config(trans->op_mode); in iwl_pcie_nic_init()
514 iwl_pcie_rx_init(trans); in iwl_pcie_nic_init()
517 if (iwl_pcie_tx_init(trans)) in iwl_pcie_nic_init()
520 if (trans->cfg->base_params->shadow_reg_enable) { in iwl_pcie_nic_init()
522 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); in iwl_pcie_nic_init()
523 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); in iwl_pcie_nic_init()
532 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) in iwl_pcie_set_hw_ready() argument
536 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_set_hw_ready()
540 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_set_hw_ready()
546 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); in iwl_pcie_set_hw_ready()
548 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); in iwl_pcie_set_hw_ready()
553 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) in iwl_pcie_prepare_card_hw() argument
559 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); in iwl_pcie_prepare_card_hw()
561 ret = iwl_pcie_set_hw_ready(trans); in iwl_pcie_prepare_card_hw()
566 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_prepare_card_hw()
572 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_prepare_card_hw()
576 ret = iwl_pcie_set_hw_ready(trans); in iwl_pcie_prepare_card_hw()
586 IWL_ERR(trans, "Couldn't prepare the card\n"); in iwl_pcie_prepare_card_hw()
594 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, in iwl_pcie_load_firmware_chunk() argument
597 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_load_firmware_chunk()
602 iwl_write_direct32(trans, in iwl_pcie_load_firmware_chunk()
606 iwl_write_direct32(trans, in iwl_pcie_load_firmware_chunk()
610 iwl_write_direct32(trans, in iwl_pcie_load_firmware_chunk()
614 iwl_write_direct32(trans, in iwl_pcie_load_firmware_chunk()
619 iwl_write_direct32(trans, in iwl_pcie_load_firmware_chunk()
625 iwl_write_direct32(trans, in iwl_pcie_load_firmware_chunk()
634 IWL_ERR(trans, "Failed to load firmware chunk!\n"); in iwl_pcie_load_firmware_chunk()
641 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, in iwl_pcie_load_section() argument
649 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", in iwl_pcie_load_section()
652 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, in iwl_pcie_load_section()
655 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); in iwl_pcie_load_section()
657 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, in iwl_pcie_load_section()
675 iwl_set_bits_prph(trans, LMPM_CHICK, in iwl_pcie_load_section()
679 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, in iwl_pcie_load_section()
683 iwl_clear_bits_prph(trans, LMPM_CHICK, in iwl_pcie_load_section()
687 IWL_ERR(trans, in iwl_pcie_load_section()
694 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); in iwl_pcie_load_section()
703 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans) in iwl_pcie_rsa_race_bug_wa() argument
712 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0); in iwl_pcie_rsa_race_bug_wa()
714 IWL_DEBUG_INFO(trans, in iwl_pcie_rsa_race_bug_wa()
720 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK); in iwl_pcie_rsa_race_bug_wa()
721 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK); in iwl_pcie_rsa_race_bug_wa()
724 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1); in iwl_pcie_rsa_race_bug_wa()
725 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS); in iwl_pcie_rsa_race_bug_wa()
727 iwl_write_prph(trans, RSA_ENABLE, 0); in iwl_pcie_rsa_race_bug_wa()
735 IWL_ERR(trans, "Failed to take ownership on secure machine\n"); in iwl_pcie_rsa_race_bug_wa()
739 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, in iwl_pcie_load_cpu_sections_8000() argument
761 IWL_DEBUG_FW(trans, in iwl_pcie_load_cpu_sections_8000()
767 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections_8000()
772 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); in iwl_pcie_load_cpu_sections_8000()
774 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); in iwl_pcie_load_cpu_sections_8000()
781 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF); in iwl_pcie_load_cpu_sections_8000()
783 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF); in iwl_pcie_load_cpu_sections_8000()
788 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, in iwl_pcie_load_cpu_sections() argument
810 IWL_DEBUG_FW(trans, in iwl_pcie_load_cpu_sections()
816 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections()
821 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) in iwl_pcie_load_cpu_sections()
822 iwl_set_bits_prph(trans, in iwl_pcie_load_cpu_sections()
834 static void iwl_pcie_apply_destination(struct iwl_trans *trans) in iwl_pcie_apply_destination() argument
836 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_apply_destination()
837 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; in iwl_pcie_apply_destination()
841 IWL_ERR(trans, in iwl_pcie_apply_destination()
845 IWL_INFO(trans, "Applying debug destination %s\n", in iwl_pcie_apply_destination()
849 iwl_pcie_alloc_fw_monitor(trans); in iwl_pcie_apply_destination()
851 IWL_WARN(trans, "PCI should have external buffer debug\n"); in iwl_pcie_apply_destination()
853 for (i = 0; i < trans->dbg_dest_reg_num; i++) { in iwl_pcie_apply_destination()
859 iwl_write32(trans, addr, val); in iwl_pcie_apply_destination()
862 iwl_set_bit(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
865 iwl_clear_bit(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
868 iwl_write_prph(trans, addr, val); in iwl_pcie_apply_destination()
871 iwl_set_bits_prph(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
874 iwl_clear_bits_prph(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
877 IWL_ERR(trans, "FW debug - unknown OP %d\n", in iwl_pcie_apply_destination()
884 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), in iwl_pcie_apply_destination()
886 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) in iwl_pcie_apply_destination()
887 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
892 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
899 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, in iwl_pcie_load_given_ucode() argument
902 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_load_given_ucode()
906 IWL_DEBUG_FW(trans, "working with %s CPU\n", in iwl_pcie_load_given_ucode()
910 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); in iwl_pcie_load_given_ucode()
916 iwl_write_prph(trans, in iwl_pcie_load_given_ucode()
921 ret = iwl_pcie_load_cpu_sections(trans, image, 2, in iwl_pcie_load_given_ucode()
929 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { in iwl_pcie_load_given_ucode()
930 iwl_pcie_alloc_fw_monitor(trans); in iwl_pcie_load_given_ucode()
933 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, in iwl_pcie_load_given_ucode()
935 iwl_write_prph(trans, MON_BUFF_END_ADDR, in iwl_pcie_load_given_ucode()
939 } else if (trans->dbg_dest_tlv) { in iwl_pcie_load_given_ucode()
940 iwl_pcie_apply_destination(trans); in iwl_pcie_load_given_ucode()
944 iwl_write32(trans, CSR_RESET, 0); in iwl_pcie_load_given_ucode()
949 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, in iwl_pcie_load_given_ucode_8000() argument
955 IWL_DEBUG_FW(trans, "working with %s CPU\n", in iwl_pcie_load_given_ucode_8000()
958 if (trans->dbg_dest_tlv) in iwl_pcie_load_given_ucode_8000()
959 iwl_pcie_apply_destination(trans); in iwl_pcie_load_given_ucode_8000()
962 ret = iwl_pcie_rsa_race_bug_wa(trans); in iwl_pcie_load_given_ucode_8000()
968 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); in iwl_pcie_load_given_ucode_8000()
971 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, in iwl_pcie_load_given_ucode_8000()
977 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 2, in iwl_pcie_load_given_ucode_8000()
985 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, in iwl_trans_pcie_start_fw() argument
992 if (iwl_pcie_prepare_card_hw(trans)) { in iwl_trans_pcie_start_fw()
993 IWL_WARN(trans, "Exit HW not ready\n"); in iwl_trans_pcie_start_fw()
997 iwl_enable_rfkill_int(trans); in iwl_trans_pcie_start_fw()
1000 hw_rfkill = iwl_is_rfkill_set(trans); in iwl_trans_pcie_start_fw()
1002 set_bit(STATUS_RFKILL, &trans->status); in iwl_trans_pcie_start_fw()
1004 clear_bit(STATUS_RFKILL, &trans->status); in iwl_trans_pcie_start_fw()
1005 iwl_trans_pcie_rf_kill(trans, hw_rfkill); in iwl_trans_pcie_start_fw()
1009 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); in iwl_trans_pcie_start_fw()
1011 ret = iwl_pcie_nic_init(trans); in iwl_trans_pcie_start_fw()
1013 IWL_ERR(trans, "Unable to init nic\n"); in iwl_trans_pcie_start_fw()
1018 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1019 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, in iwl_trans_pcie_start_fw()
1023 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); in iwl_trans_pcie_start_fw()
1024 iwl_enable_interrupts(trans); in iwl_trans_pcie_start_fw()
1027 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1028 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1031 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_start_fw()
1032 return iwl_pcie_load_given_ucode_8000(trans, fw); in iwl_trans_pcie_start_fw()
1034 return iwl_pcie_load_given_ucode(trans, fw); in iwl_trans_pcie_start_fw()
1037 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) in iwl_trans_pcie_fw_alive() argument
1039 iwl_pcie_reset_ict(trans); in iwl_trans_pcie_fw_alive()
1040 iwl_pcie_tx_start(trans, scd_addr); in iwl_trans_pcie_fw_alive()
1043 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) in iwl_trans_pcie_stop_device() argument
1045 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_stop_device()
1048 was_hw_rfkill = iwl_is_rfkill_set(trans); in iwl_trans_pcie_stop_device()
1052 iwl_disable_interrupts(trans); in iwl_trans_pcie_stop_device()
1056 iwl_pcie_disable_ict(trans); in iwl_trans_pcie_stop_device()
1065 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { in iwl_trans_pcie_stop_device()
1066 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n"); in iwl_trans_pcie_stop_device()
1067 iwl_pcie_tx_stop(trans); in iwl_trans_pcie_stop_device()
1068 iwl_pcie_rx_stop(trans); in iwl_trans_pcie_stop_device()
1071 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) { in iwl_trans_pcie_stop_device()
1072 iwl_write_prph(trans, APMG_CLK_DIS_REG, in iwl_trans_pcie_stop_device()
1079 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_stop_device()
1083 iwl_pcie_apm_stop(trans, false); in iwl_trans_pcie_stop_device()
1086 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in iwl_trans_pcie_stop_device()
1097 iwl_disable_interrupts(trans); in iwl_trans_pcie_stop_device()
1102 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); in iwl_trans_pcie_stop_device()
1103 clear_bit(STATUS_INT_ENABLED, &trans->status); in iwl_trans_pcie_stop_device()
1104 clear_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_stop_device()
1105 clear_bit(STATUS_RFKILL, &trans->status); in iwl_trans_pcie_stop_device()
1111 iwl_enable_rfkill_int(trans); in iwl_trans_pcie_stop_device()
1125 hw_rfkill = iwl_is_rfkill_set(trans); in iwl_trans_pcie_stop_device()
1127 set_bit(STATUS_RFKILL, &trans->status); in iwl_trans_pcie_stop_device()
1129 clear_bit(STATUS_RFKILL, &trans->status); in iwl_trans_pcie_stop_device()
1131 iwl_trans_pcie_rf_kill(trans, hw_rfkill); in iwl_trans_pcie_stop_device()
1134 iwl_pcie_prepare_card_hw(trans); in iwl_trans_pcie_stop_device()
1137 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) in iwl_trans_pcie_rf_kill() argument
1139 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) in iwl_trans_pcie_rf_kill()
1140 iwl_trans_pcie_stop_device(trans, true); in iwl_trans_pcie_rf_kill()
1143 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test) in iwl_trans_pcie_d3_suspend() argument
1145 iwl_disable_interrupts(trans); in iwl_trans_pcie_d3_suspend()
1154 iwl_pcie_disable_ict(trans); in iwl_trans_pcie_d3_suspend()
1156 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_suspend()
1158 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_suspend()
1166 iwl_trans_pcie_tx_reset(trans); in iwl_trans_pcie_d3_suspend()
1168 iwl_pcie_set_pwr(trans, true); in iwl_trans_pcie_d3_suspend()
1171 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, in iwl_trans_pcie_d3_resume() argument
1179 iwl_enable_interrupts(trans); in iwl_trans_pcie_d3_resume()
1189 iwl_pcie_reset_ict(trans); in iwl_trans_pcie_d3_resume()
1191 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); in iwl_trans_pcie_d3_resume()
1192 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_trans_pcie_d3_resume()
1194 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_d3_resume()
1197 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_resume()
1202 IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); in iwl_trans_pcie_d3_resume()
1206 iwl_pcie_set_pwr(trans, false); in iwl_trans_pcie_d3_resume()
1208 iwl_trans_pcie_tx_reset(trans); in iwl_trans_pcie_d3_resume()
1210 ret = iwl_pcie_rx_init(trans); in iwl_trans_pcie_d3_resume()
1212 IWL_ERR(trans, "Failed to resume the device (RX reset)\n"); in iwl_trans_pcie_d3_resume()
1216 val = iwl_read32(trans, CSR_RESET); in iwl_trans_pcie_d3_resume()
1225 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) in iwl_trans_pcie_start_hw() argument
1230 err = iwl_pcie_prepare_card_hw(trans); in iwl_trans_pcie_start_hw()
1232 IWL_ERR(trans, "Error while preparing HW: %d\n", err); in iwl_trans_pcie_start_hw()
1237 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in iwl_trans_pcie_start_hw()
1241 iwl_pcie_apm_init(trans); in iwl_trans_pcie_start_hw()
1244 iwl_enable_rfkill_int(trans); in iwl_trans_pcie_start_hw()
1246 hw_rfkill = iwl_is_rfkill_set(trans); in iwl_trans_pcie_start_hw()
1248 set_bit(STATUS_RFKILL, &trans->status); in iwl_trans_pcie_start_hw()
1250 clear_bit(STATUS_RFKILL, &trans->status); in iwl_trans_pcie_start_hw()
1251 iwl_trans_pcie_rf_kill(trans, hw_rfkill); in iwl_trans_pcie_start_hw()
1256 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) in iwl_trans_pcie_op_mode_leave() argument
1258 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_op_mode_leave()
1262 iwl_disable_interrupts(trans); in iwl_trans_pcie_op_mode_leave()
1265 iwl_pcie_apm_stop(trans, true); in iwl_trans_pcie_op_mode_leave()
1268 iwl_disable_interrupts(trans); in iwl_trans_pcie_op_mode_leave()
1271 iwl_pcie_disable_ict(trans); in iwl_trans_pcie_op_mode_leave()
1274 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) in iwl_trans_pcie_write8() argument
1276 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write8()
1279 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) in iwl_trans_pcie_write32() argument
1281 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write32()
1284 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) in iwl_trans_pcie_read32() argument
1286 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_read32()
1289 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) in iwl_trans_pcie_read_prph() argument
1291 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, in iwl_trans_pcie_read_prph()
1293 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); in iwl_trans_pcie_read_prph()
1296 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_write_prph() argument
1299 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, in iwl_trans_pcie_write_prph()
1301 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); in iwl_trans_pcie_write_prph()
1310 static void iwl_trans_pcie_configure(struct iwl_trans *trans, in iwl_trans_pcie_configure() argument
1313 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_configure()
1344 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) { in iwl_trans_pcie_configure()
1346 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi, in iwl_trans_pcie_configure()
1352 void iwl_trans_pcie_free(struct iwl_trans *trans) in iwl_trans_pcie_free() argument
1354 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_free()
1358 iwl_pcie_tx_free(trans); in iwl_trans_pcie_free()
1359 iwl_pcie_rx_free(trans); in iwl_trans_pcie_free()
1361 free_irq(trans_pcie->pci_dev->irq, trans); in iwl_trans_pcie_free()
1362 iwl_pcie_free_ict(trans); in iwl_trans_pcie_free()
1368 kmem_cache_destroy(trans->dev_cmd_pool); in iwl_trans_pcie_free()
1373 iwl_pcie_free_fw_monitor(trans); in iwl_trans_pcie_free()
1375 kfree(trans); in iwl_trans_pcie_free()
1378 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) in iwl_trans_pcie_set_pmi() argument
1381 set_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_set_pmi()
1383 clear_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_set_pmi()
1386 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent, in iwl_trans_pcie_grab_nic_access() argument
1390 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_grab_nic_access()
1398 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_grab_nic_access()
1400 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_grab_nic_access()
1422 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_grab_nic_access()
1427 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); in iwl_trans_pcie_grab_nic_access()
1429 u32 val = iwl_read32(trans, CSR_GP_CNTRL); in iwl_trans_pcie_grab_nic_access()
1447 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, in iwl_trans_pcie_release_nic_access() argument
1450 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_release_nic_access()
1463 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_release_nic_access()
1476 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_read_mem() argument
1483 if (iwl_trans_grab_nic_access(trans, false, &flags)) { in iwl_trans_pcie_read_mem()
1484 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); in iwl_trans_pcie_read_mem()
1486 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); in iwl_trans_pcie_read_mem()
1487 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_read_mem()
1494 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_write_mem() argument
1501 if (iwl_trans_grab_nic_access(trans, false, &flags)) { in iwl_trans_pcie_write_mem()
1502 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); in iwl_trans_pcie_write_mem()
1504 iwl_write32(trans, HBUS_TARG_MEM_WDAT, in iwl_trans_pcie_write_mem()
1506 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_write_mem()
1513 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, in iwl_trans_pcie_freeze_txq_timer() argument
1517 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_freeze_txq_timer()
1531 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", in iwl_trans_pcie_freeze_txq_timer()
1569 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) in iwl_trans_pcie_wait_txq_empty() argument
1571 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_wait_txq_empty()
1581 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { in iwl_trans_pcie_wait_txq_empty()
1591 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt); in iwl_trans_pcie_wait_txq_empty()
1609 IWL_ERR(trans, in iwl_trans_pcie_wait_txq_empty()
1614 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt); in iwl_trans_pcie_wait_txq_empty()
1620 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", in iwl_trans_pcie_wait_txq_empty()
1625 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); in iwl_trans_pcie_wait_txq_empty()
1627 iwl_print_hex_error(trans, buf, sizeof(buf)); in iwl_trans_pcie_wait_txq_empty()
1630 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, in iwl_trans_pcie_wait_txq_empty()
1631 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); in iwl_trans_pcie_wait_txq_empty()
1633 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { in iwl_trans_pcie_wait_txq_empty()
1634 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); in iwl_trans_pcie_wait_txq_empty()
1638 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + in iwl_trans_pcie_wait_txq_empty()
1646 IWL_ERR(trans, in iwl_trans_pcie_wait_txq_empty()
1649 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) & in iwl_trans_pcie_wait_txq_empty()
1651 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); in iwl_trans_pcie_wait_txq_empty()
1657 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, in iwl_trans_pcie_set_bits_mask() argument
1660 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_set_bits_mask()
1664 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); in iwl_trans_pcie_set_bits_mask()
1668 void iwl_trans_pcie_ref(struct iwl_trans *trans) in iwl_trans_pcie_ref() argument
1670 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_ref()
1677 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count); in iwl_trans_pcie_ref()
1682 void iwl_trans_pcie_unref(struct iwl_trans *trans) in iwl_trans_pcie_unref() argument
1684 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_unref()
1691 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count); in iwl_trans_pcie_unref()
1734 void iwl_pcie_dump_csr(struct iwl_trans *trans) in iwl_pcie_dump_csr() argument
1763 IWL_ERR(trans, "CSR values:\n"); in iwl_pcie_dump_csr()
1764 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " in iwl_pcie_dump_csr()
1767 IWL_ERR(trans, " %25s: 0X%08x\n", in iwl_pcie_dump_csr()
1769 iwl_read32(trans, csr_tbl[i])); in iwl_pcie_dump_csr()
1776 if (!debugfs_create_file(#name, mode, parent, trans, \
1808 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_tx_queue_read() local
1809 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_tx_queue_read()
1818 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; in iwl_dbgfs_tx_queue_read()
1827 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { in iwl_dbgfs_tx_queue_read()
1847 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rx_queue_read() local
1848 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rx_queue_read()
1878 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_read() local
1879 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_interrupt_read()
1936 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_write() local
1937 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_interrupt_write()
1960 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_csr_write() local
1972 iwl_pcie_dump_csr(trans); in iwl_dbgfs_csr_write()
1981 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_fh_reg_read() local
1985 ret = iwl_dump_fh(trans, &buf); in iwl_dbgfs_fh_reg_read()
2005 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, in iwl_trans_pcie_dbgfs_register() argument
2016 IWL_ERR(trans, "failed to create the trans debugfs entry\n"); in iwl_trans_pcie_dbgfs_register()
2020 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, in iwl_trans_pcie_dbgfs_register() argument
2137 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans, in iwl_trans_pcie_dump_prph() argument
2144 if (!iwl_trans_grab_nic_access(trans, false, &flags)) in iwl_trans_pcie_dump_prph()
2166 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, in iwl_trans_pcie_dump_prph()
2171 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_dump_prph()
2178 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, in iwl_trans_pcie_dump_csr() argument
2190 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); in iwl_trans_pcie_dump_csr()
2197 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, in iwl_trans_pcie_fh_regs_dump() argument
2205 if (!iwl_trans_grab_nic_access(trans, false, &flags)) in iwl_trans_pcie_fh_regs_dump()
2213 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); in iwl_trans_pcie_fh_regs_dump()
2215 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_fh_regs_dump()
2223 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans) in iwl_trans_pcie_dump_data() argument
2225 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_data()
2262 } else if (trans->dbg_dest_tlv) { in iwl_trans_pcie_dump_data()
2265 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); in iwl_trans_pcie_dump_data()
2266 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); in iwl_trans_pcie_dump_data()
2268 base = iwl_read_prph(trans, base) << in iwl_trans_pcie_dump_data()
2269 trans->dbg_dest_tlv->base_shift; in iwl_trans_pcie_dump_data()
2270 end = iwl_read_prph(trans, end) << in iwl_trans_pcie_dump_data()
2271 trans->dbg_dest_tlv->end_shift; in iwl_trans_pcie_dump_data()
2274 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_dump_data()
2275 end += (1 << trans->dbg_dest_tlv->end_shift); in iwl_trans_pcie_dump_data()
2316 len += iwl_trans_pcie_dump_prph(trans, &data); in iwl_trans_pcie_dump_data()
2317 len += iwl_trans_pcie_dump_csr(trans, &data); in iwl_trans_pcie_dump_data()
2318 len += iwl_trans_pcie_fh_regs_dump(trans, &data); in iwl_trans_pcie_dump_data()
2322 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || in iwl_trans_pcie_dump_data()
2323 trans->dbg_dest_tlv) { in iwl_trans_pcie_dump_data()
2328 if (trans->dbg_dest_tlv) { in iwl_trans_pcie_dump_data()
2330 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); in iwl_trans_pcie_dump_data()
2331 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); in iwl_trans_pcie_dump_data()
2332 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); in iwl_trans_pcie_dump_data()
2342 cpu_to_le32(iwl_read_prph(trans, write_ptr)); in iwl_trans_pcie_dump_data()
2344 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); in iwl_trans_pcie_dump_data()
2346 cpu_to_le32(iwl_read_prph(trans, base)); in iwl_trans_pcie_dump_data()
2359 dma_sync_single_for_cpu(trans->dev, in iwl_trans_pcie_dump_data()
2375 base = iwl_read_prph(trans, base) << in iwl_trans_pcie_dump_data()
2376 trans->dbg_dest_tlv->base_shift; in iwl_trans_pcie_dump_data()
2377 iwl_trans_read_mem(trans, base, fw_mon_data->data, in iwl_trans_pcie_dump_data()
2437 struct iwl_trans *trans; in iwl_trans_pcie_alloc() local
2441 trans = kzalloc(sizeof(struct iwl_trans) + in iwl_trans_pcie_alloc()
2443 if (!trans) { in iwl_trans_pcie_alloc()
2448 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_alloc()
2450 trans->ops = &trans_ops_pcie; in iwl_trans_pcie_alloc()
2451 trans->cfg = cfg; in iwl_trans_pcie_alloc()
2452 trans_lockdep_init(trans); in iwl_trans_pcie_alloc()
2453 trans_pcie->trans = trans; in iwl_trans_pcie_alloc()
2508 trans->dev = &pdev->dev; in iwl_trans_pcie_alloc()
2510 iwl_disable_interrupts(trans); in iwl_trans_pcie_alloc()
2523 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); in iwl_trans_pcie_alloc()
2530 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { in iwl_trans_pcie_alloc()
2534 trans->hw_rev = (trans->hw_rev & 0xfff0) | in iwl_trans_pcie_alloc()
2535 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); in iwl_trans_pcie_alloc()
2537 ret = iwl_pcie_prepare_card_hw(trans); in iwl_trans_pcie_alloc()
2539 IWL_WARN(trans, "Exit HW not ready\n"); in iwl_trans_pcie_alloc()
2547 iwl_set_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_alloc()
2551 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_alloc()
2556 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); in iwl_trans_pcie_alloc()
2560 if (iwl_trans_grab_nic_access(trans, false, &flags)) { in iwl_trans_pcie_alloc()
2563 hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG); in iwl_trans_pcie_alloc()
2565 __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step); in iwl_trans_pcie_alloc()
2566 hw_step = __iwl_read_prph(trans, AUX_MISC_REG); in iwl_trans_pcie_alloc()
2569 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | in iwl_trans_pcie_alloc()
2571 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_alloc()
2575 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; in iwl_trans_pcie_alloc()
2576 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), in iwl_trans_pcie_alloc()
2582 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name), in iwl_trans_pcie_alloc()
2583 "iwl_cmd_pool:%s", dev_name(trans->dev)); in iwl_trans_pcie_alloc()
2585 trans->dev_cmd_headroom = 0; in iwl_trans_pcie_alloc()
2586 trans->dev_cmd_pool = in iwl_trans_pcie_alloc()
2587 kmem_cache_create(trans->dev_cmd_pool_name, in iwl_trans_pcie_alloc()
2589 + trans->dev_cmd_headroom, in iwl_trans_pcie_alloc()
2594 if (!trans->dev_cmd_pool) { in iwl_trans_pcie_alloc()
2599 if (iwl_pcie_alloc_ict(trans)) in iwl_trans_pcie_alloc()
2604 IRQF_SHARED, DRV_NAME, trans); in iwl_trans_pcie_alloc()
2606 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); in iwl_trans_pcie_alloc()
2611 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND; in iwl_trans_pcie_alloc()
2613 return trans; in iwl_trans_pcie_alloc()
2616 iwl_pcie_free_ict(trans); in iwl_trans_pcie_alloc()
2618 kmem_cache_destroy(trans->dev_cmd_pool); in iwl_trans_pcie_alloc()
2626 kfree(trans); in iwl_trans_pcie_alloc()