Lines Matching refs:iwl_set_bit
198 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); in iwl_pcie_apm_config()
227 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, in iwl_pcie_apm_init()
234 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, in iwl_pcie_apm_init()
238 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); in iwl_pcie_apm_init()
244 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_init()
251 iwl_set_bit(trans, CSR_ANA_PLL_CFG, in iwl_pcie_apm_init()
258 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_apm_init()
341 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in iwl_pcie_apm_lp_xtal_enable()
349 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_apm_lp_xtal_enable()
388 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in iwl_pcie_apm_lp_xtal_enable()
407 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_lp_xtal_enable()
437 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); in iwl_pcie_apm_stop_master()
463 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_apm_stop()
465 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_stop()
486 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in iwl_pcie_apm_stop()
522 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); in iwl_pcie_nic_init()
536 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_set_hw_ready()
546 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); in iwl_pcie_set_hw_ready()
566 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_prepare_card_hw()
572 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_prepare_card_hw()
862 iwl_set_bit(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
1191 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); in iwl_trans_pcie_d3_resume()
1192 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_trans_pcie_d3_resume()
2547 iwl_set_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_alloc()