Lines Matching refs:ath10k_pci_write32
351 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, in ath10k_pci_disable_and_clear_legacy_irq()
353 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, in ath10k_pci_disable_and_clear_legacy_irq()
364 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + in ath10k_pci_enable_legacy_irq()
1177 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS, val); in ath10k_pci_irq_msi_fw_mask()
1187 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS, val); in ath10k_pci_irq_msi_fw_unmask()
1515 ath10k_pci_write32(ar, addr, val); in ath10k_pci_wake_target_cpu()
1757 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); in ath10k_pci_fw_crashed_clear()
1784 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); in ath10k_pci_warm_reset_cpu()
1788 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, in ath10k_pci_warm_reset_cpu()
1799 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, in ath10k_pci_warm_reset_ce()
1802 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, in ath10k_pci_warm_reset_ce()
1812 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + in ath10k_pci_warm_reset_clear_lf()
2108 .write32 = ath10k_pci_write32,
2368 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, in ath10k_pci_init_irq()
2376 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, in ath10k_pci_deinit_irq_legacy()