447 		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);  in sh_eth_set_duplex()
449 		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);  in sh_eth_set_duplex()
459 		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);  in sh_eth_set_rate_r8a777x()
462 		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);  in sh_eth_set_rate_r8a777x()
524 		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);  in sh_eth_set_rate_sh7724()
527 		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);  in sh_eth_set_rate_sh7724()
882 		if (!(sh_eth_read(ndev, EDMR) & 0x3))  in sh_eth_check_reset()
901 		sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,  in sh_eth_reset()
926 		sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,  in sh_eth_reset()
929 		sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,  in sh_eth_reset()
990 		ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);  in read_mac_address()
991 		ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;  in read_mac_address()
992 		ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;  in read_mac_address()
993 		ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);  in read_mac_address()
994 		ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;  in read_mac_address()
995 		ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);  in read_mac_address()
1332 	sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);  in sh_eth_dev_init()
1339 	val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |  in sh_eth_dev_init()
1558 	if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {  in sh_eth_rx()
1562 			u32 count = (sh_eth_read(ndev, RDFAR) -  in sh_eth_rx()
1563 				     sh_eth_read(ndev, RDLAR)) >> 4;  in sh_eth_rx()
1579 	sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &  in sh_eth_rcv_snd_disable()
1586 	sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |  in sh_eth_rcv_snd_enable()
1599 		felic_stat = sh_eth_read(ndev, ECSR);  in sh_eth_error()
1608 				link_stat = (sh_eth_read(ndev, PSR));  in sh_eth_error()
1616 				sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &  in sh_eth_error()
1619 				sh_eth_write(ndev, sh_eth_read(ndev, ECSR),  in sh_eth_error()
1621 				sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |  in sh_eth_error()
1679 		u32 edtrr = sh_eth_read(ndev, EDTRR);  in sh_eth_error()
1709 	intr_status = sh_eth_read(ndev, EESR);  in sh_eth_interrupt()
1715 	intr_enable = sh_eth_read(ndev, EESIPR);  in sh_eth_interrupt()
1771 		intr_status = sh_eth_read(ndev, EESR);  in sh_eth_poll()
1813 				     sh_eth_read(ndev, ECMR) & ~ECMR_TXF,  in sh_eth_adjust_link()
1991 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))  in __sh_eth_get_regs()
2347 		  sh_eth_read(ndev, EESR));  in sh_eth_tx_timeout()
2414 	if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))  in sh_eth_start_xmit()
2428 	u32 delta = sh_eth_read(ndev, reg);  in sh_eth_update_stat()
2762 	ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;  in sh_eth_set_rx_mode()