Lines Matching refs:io
1270 void __iomem *io; member
1501 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS); in hw_ack_intr()
1507 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE); in hw_dis_intr()
1508 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE); in hw_dis_intr()
1514 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE); in hw_set_intr()
1532 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE); in hw_turn_off_intr()
1534 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE); in hw_turn_off_intr()
1558 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE); in hw_ena_intr_bit()
1560 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE); in hw_ena_intr_bit()
1565 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS); in hw_read_intr()
1661 dummy = readw(hw->io + reg); \
1683 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); in sw_r_table()
1685 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); in sw_r_table()
1711 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET); in sw_w_table_64()
1712 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET); in sw_w_table_64()
1714 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); in sw_w_table_64()
1809 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); in port_r_mib_cnt()
1813 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); in port_r_mib_cnt()
1850 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); in port_r_mib_pkt()
1852 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); in port_r_mib_pkt()
1949 data = readw(hw->io + addr); in port_chk()
1971 data = readw(hw->io + addr); in port_cfg()
1976 writew(data, hw->io + addr); in port_cfg()
1996 data = readw(hw->io + addr); in port_chk_shift()
2017 data = readw(hw->io + addr); in port_cfg_shift()
2023 writew(data, hw->io + addr); in port_cfg_shift()
2041 *data = readb(hw->io + addr); in port_r8()
2059 *data = readw(hw->io + addr); in port_r16()
2077 writew(data, hw->io + addr); in port_w16()
2095 data = readw(hw->io + addr); in sw_chk()
2112 data = readw(hw->io + addr); in sw_cfg()
2117 writew(data, hw->io + addr); in sw_cfg()
2155 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); in sw_cfg_broad_storm()
2158 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET); in sw_cfg_broad_storm()
2173 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); in sw_get_broad_storm()
2254 writel(0, hw->io + addr); in sw_dis_prio_rate()
2637 *vid = readw(hw->io + addr); in port_get_def_vid()
2682 data = readb(hw->io + addr); in sw_cfg_port_base_vlan()
2685 writeb(data, hw->io + addr); in sw_cfg_port_base_vlan()
2702 mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i); in sw_get_addr()
2703 mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i); in sw_get_addr()
2719 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i); in sw_set_addr()
2720 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i); in sw_set_addr()
2735 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); in sw_set_global_ctrl()
2737 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET); in sw_set_global_ctrl()
2739 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET); in sw_set_global_ctrl()
2752 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET); in sw_set_global_ctrl()
2754 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET); in sw_set_global_ctrl()
2758 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET); in sw_set_global_ctrl()
2906 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET); in hw_r_phy_ctrl()
2911 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET); in hw_w_phy_ctrl()
2916 *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET); in hw_r_phy_link_stat()
2921 *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET); in hw_r_phy_auto_neg()
2926 writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET); in hw_w_phy_auto_neg()
2931 *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET); in hw_r_phy_rem_cap()
2936 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET); in hw_r_phy_crossover()
2941 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET); in hw_w_phy_crossover()
2946 *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET); in hw_r_phy_polarity()
2951 writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET); in hw_w_phy_polarity()
2956 *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET); in hw_r_phy_link_md()
2961 writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET); in hw_w_phy_link_md()
2978 *val = readw(hw->io + phy); in hw_r_phy()
2995 writew(val, hw->io + phy); in hw_w_phy()
3018 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); in drop_gpio()
3020 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET); in drop_gpio()
3027 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); in raise_gpio()
3029 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET); in raise_gpio()
3036 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); in state_gpio()
3229 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); in set_flow_ctrl()
3231 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); in set_flow_ctrl()
3274 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); in port_cfg_change()
3546 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET); in hw_cfg_wol()
3551 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET); in hw_cfg_wol()
3582 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i); in hw_set_wol_frame()
3583 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i); in hw_set_wol_frame()
3595 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i in hw_set_wol_frame()
3608 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len - in hw_set_wol_frame()
3612 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i); in hw_set_wol_frame()
3724 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET); in hw_init()
3727 data = readw(hw->io + KS884X_CHIP_ID_OFFSET); in hw_init()
3755 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET); in hw_reset()
3761 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET); in hw_reset()
3776 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET); in hw_setup()
3779 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET); in hw_setup()
3872 writel(tx_addr, hw->io + KS_DMA_TX_ADDR); in hw_set_desc_base()
3873 writel(rx_addr, hw->io + KS_DMA_RX_ADDR); in hw_set_desc_base()
3885 writel(DMA_START, hw->io + KS_DMA_RX_START); in hw_resume_rx()
3896 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); in hw_start_rx()
3901 writel(DMA_START, hw->io + KS_DMA_RX_START); in hw_start_rx()
3920 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL); in hw_stop_rx()
3931 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); in hw_start_tx()
3942 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL); in hw_stop_tx()
4029 writel(0, hw->io + KS_DMA_TX_START); in hw_send_pkt()
4053 hw->io + KS884X_ADDR_0_OFFSET + i); in hw_set_addr()
4069 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io + in hw_read_addr()
4103 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO); in hw_ena_add_addr()
4104 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI); in hw_ena_add_addr()
4113 writel(0, hw->io + ADD_ADDR_INCR * i + in hw_set_add_addr()
4148 writel(0, hw->io + ADD_ADDR_INCR * i + in hw_del_addr()
4169 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i); in hw_clr_multicast()
4197 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET + in hw_set_grp_addr()
4272 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET); in sw_enable()
5299 data = readl(hw->io + KS_DMA_TX_CTRL); in netdev_intr()
5428 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET); in hw_cfg_huge_frame()
5433 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET); in hw_cfg_huge_frame()
6151 *buf = readl(hw->io + len); in netdev_get_regs()
6597 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); in netdev_set_features()
6965 hw->io = ioremap(reg_base, reg_len); in pcidev_init()
6966 if (!hw->io) in pcidev_init()
6980 dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq); in pcidev_init()
7088 dev->mem_start = (unsigned long) hw->io; in pcidev_init()
7124 iounmap(hw->io); in pcidev_init()
7147 if (hw_priv->hw.io) in pcidev_exit()
7148 iounmap(hw_priv->hw.io); in pcidev_exit()