862 	union mvpp2_prs_sram_entry sram;  member
1007 		mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);  in mvpp2_prs_hw_write()
1034 		pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));  in mvpp2_prs_hw_read()
1173 	pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));  in mvpp2_prs_sram_bits_set()
1180 	pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));  in mvpp2_prs_sram_bits_clear()
1207 	return pe->sram.word[MVPP2_PRS_SRAM_RI_WORD];  in mvpp2_prs_sram_ri_get()
1239 	bits = (pe->sram.byte[ai_off] >> ai_shift) |  in mvpp2_prs_sram_ai_get()
1240 	       (pe->sram.byte[ai_en_off] << (8 - ai_shift));  in mvpp2_prs_sram_ai_get()
1273 	pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =  in mvpp2_prs_sram_shift_set()
1304 	pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +  in mvpp2_prs_sram_offset_set()
1307 	pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +  in mvpp2_prs_sram_offset_set()
1321 	pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +  in mvpp2_prs_sram_offset_set()
1326 	pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +  in mvpp2_prs_sram_offset_set()
1953 	pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;  in mvpp2_prs_ip4_proto()
1954 	pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;  in mvpp2_prs_ip4_proto()
2405 	pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;  in mvpp2_prs_etype_init()
2406 	pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;  in mvpp2_prs_etype_init()
2606 	pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;  in mvpp2_prs_pppoe_init()
2607 	pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;  in mvpp2_prs_pppoe_init()