Lines Matching refs:port
35 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) argument
36 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) argument
41 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) argument
60 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) argument
61 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) argument
62 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) argument
63 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) argument
64 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
65 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) argument
66 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) argument
67 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
80 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) argument
90 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) argument
93 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) argument
95 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) argument
156 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) argument
159 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) argument
168 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) argument
246 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) argument
253 #define MVPP2_MIB_COUNTERS_BASE(port) (0x1000 + ((port) >> 1) * \ argument
254 0x400 + (port) * 0x400)
606 #define MVPP2_BM_SWF_LONG_POOL(port) ((port > 2) ? 2 : port) argument
843 int port; member
975 static inline int mvpp2_egress_port(struct mvpp2_port *port) in mvpp2_egress_port() argument
977 return MVPP2_MAX_TCONT + port->id; in mvpp2_egress_port()
981 static inline int mvpp2_txq_phys(int port, int txq) in mvpp2_txq_phys() argument
983 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; in mvpp2_txq_phys()
1074 unsigned int port, bool add) in mvpp2_prs_tcam_port_set() argument
1079 pe->tcam.byte[enable_off] &= ~(1 << port); in mvpp2_prs_tcam_port_set()
1081 pe->tcam.byte[enable_off] |= 1 << port; in mvpp2_prs_tcam_port_set()
1387 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add) in mvpp2_prs_mac_drop_all_set() argument
1416 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
1422 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add) in mvpp2_prs_mac_promisc_set() argument
1457 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
1463 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index, in mvpp2_prs_mac_multi_set() argument
1506 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_multi_set()
1512 static void mvpp2_prs_dsa_tag_set(struct mvpp2 *priv, int port, bool add, in mvpp2_prs_dsa_tag_set() argument
1565 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_set()
1571 static void mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2 *priv, int port, in mvpp2_prs_dsa_tag_ethertype_set() argument
1634 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_ethertype_set()
2100 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first, in mvpp2_prs_hw_port_init() argument
2107 val &= ~MVPP2_PRS_PORT_LU_MASK(port); in mvpp2_prs_hw_port_init()
2108 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first); in mvpp2_prs_hw_port_init()
2112 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port)); in mvpp2_prs_hw_port_init()
2113 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port); in mvpp2_prs_hw_port_init()
2114 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max); in mvpp2_prs_hw_port_init()
2115 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); in mvpp2_prs_hw_port_init()
2120 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port)); in mvpp2_prs_hw_port_init()
2121 val &= ~MVPP2_PRS_INIT_OFF_MASK(port); in mvpp2_prs_hw_port_init()
2122 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset); in mvpp2_prs_hw_port_init()
2123 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); in mvpp2_prs_hw_port_init()
2130 int port; in mvpp2_prs_def_flow_init() local
2132 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_prs_def_flow_init()
2135 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
2141 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
3010 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port, in mvpp2_prs_mac_da_accept() argument
3019 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, in mvpp2_prs_mac_da_accept()
3054 mvpp2_prs_tcam_port_set(pe, port, add); in mvpp2_prs_mac_da_accept()
3106 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_prs_update_mac_da() local
3110 err = mvpp2_prs_mac_da_accept(port->priv, port->id, dev->dev_addr, in mvpp2_prs_update_mac_da()
3116 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true); in mvpp2_prs_update_mac_da()
3127 static void mvpp2_prs_mcast_del_all(struct mvpp2 *priv, int port) in mvpp2_prs_mcast_del_all() argument
3152 mvpp2_prs_mac_da_accept(priv, port, da, false); in mvpp2_prs_mcast_del_all()
3156 static int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type) in mvpp2_prs_tag_mode_set() argument
3161 mvpp2_prs_dsa_tag_set(priv, port, true, in mvpp2_prs_tag_mode_set()
3163 mvpp2_prs_dsa_tag_set(priv, port, true, in mvpp2_prs_tag_mode_set()
3166 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3168 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3174 mvpp2_prs_dsa_tag_set(priv, port, true, in mvpp2_prs_tag_mode_set()
3176 mvpp2_prs_dsa_tag_set(priv, port, true, in mvpp2_prs_tag_mode_set()
3179 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3181 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3188 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3190 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3192 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3194 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3207 static int mvpp2_prs_def_flow(struct mvpp2_port *port) in mvpp2_prs_def_flow() argument
3212 pe = mvpp2_prs_flow_find(port->priv, port->id); in mvpp2_prs_def_flow()
3217 tid = mvpp2_prs_tcam_first_free(port->priv, in mvpp2_prs_def_flow()
3231 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
3235 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
3238 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); in mvpp2_prs_def_flow()
3239 mvpp2_prs_hw_write(port->priv, pe); in mvpp2_prs_def_flow()
3297 static void mvpp2_cls_port_config(struct mvpp2_port *port) in mvpp2_cls_port_config() argument
3303 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); in mvpp2_cls_port_config()
3304 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); in mvpp2_cls_port_config()
3305 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); in mvpp2_cls_port_config()
3310 le.lkpid = port->id; in mvpp2_cls_port_config()
3316 le.data |= port->first_rxq; in mvpp2_cls_port_config()
3322 mvpp2_cls_lookup_write(port->priv, &le); in mvpp2_cls_port_config()
3326 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port) in mvpp2_cls_oversize_rxq_set() argument
3330 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), in mvpp2_cls_oversize_rxq_set()
3331 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK); in mvpp2_cls_oversize_rxq_set()
3333 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), in mvpp2_cls_oversize_rxq_set()
3334 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS)); in mvpp2_cls_oversize_rxq_set()
3336 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set()
3337 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); in mvpp2_cls_oversize_rxq_set()
3338 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
3489 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, in mvpp2_rxq_long_pool_set() argument
3496 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_long_pool_set()
3498 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_long_pool_set()
3503 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
3507 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, in mvpp2_rxq_short_pool_set() argument
3514 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_short_pool_set()
3516 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_short_pool_set()
3521 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_short_pool_set()
3525 static struct sk_buff *mvpp2_skb_alloc(struct mvpp2_port *port, in mvpp2_skb_alloc() argument
3537 phys_addr = dma_map_single(port->dev->dev.parent, skb->head, in mvpp2_skb_alloc()
3540 if (unlikely(dma_mapping_error(port->dev->dev.parent, phys_addr))) { in mvpp2_skb_alloc()
3567 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, in mvpp2_bm_pool_put() argument
3570 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr); in mvpp2_bm_pool_put()
3571 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr); in mvpp2_bm_pool_put()
3575 static void mvpp2_bm_pool_mc_put(struct mvpp2_port *port, int pool, in mvpp2_bm_pool_mc_put() argument
3582 mvpp2_write(port->priv, MVPP2_BM_MC_RLS_REG, val); in mvpp2_bm_pool_mc_put()
3584 mvpp2_bm_pool_put(port, pool, in mvpp2_bm_pool_mc_put()
3590 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm, in mvpp2_pool_refill() argument
3595 mvpp2_bm_pool_put(port, pool, phys_addr, cookie); in mvpp2_pool_refill()
3599 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, in mvpp2_bm_bufs_add() argument
3612 netdev_err(port->dev, in mvpp2_bm_bufs_add()
3620 skb = mvpp2_skb_alloc(port, bm_pool, &phys_addr, GFP_KERNEL); in mvpp2_bm_bufs_add()
3624 mvpp2_pool_refill(port, bm, (u32)phys_addr, (u32)skb); in mvpp2_bm_bufs_add()
3631 netdev_dbg(port->dev, in mvpp2_bm_bufs_add()
3636 netdev_dbg(port->dev, in mvpp2_bm_bufs_add()
3647 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, in mvpp2_bm_pool_use() argument
3651 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; in mvpp2_bm_pool_use()
3655 netdev_err(port->dev, "mixing pool types is forbidden\n"); in mvpp2_bm_pool_use()
3680 mvpp2_bm_bufs_free(port->priv, new_pool); in mvpp2_bm_pool_use()
3685 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); in mvpp2_bm_pool_use()
3695 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, in mvpp2_bm_pool_use()
3704 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) in mvpp2_swf_bm_pool_init() argument
3709 if (!port->pool_long) { in mvpp2_swf_bm_pool_init()
3710 port->pool_long = in mvpp2_swf_bm_pool_init()
3711 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id), in mvpp2_swf_bm_pool_init()
3713 port->pkt_size); in mvpp2_swf_bm_pool_init()
3714 if (!port->pool_long) in mvpp2_swf_bm_pool_init()
3717 spin_lock_irqsave(&port->pool_long->lock, flags); in mvpp2_swf_bm_pool_init()
3718 port->pool_long->port_map |= (1 << port->id); in mvpp2_swf_bm_pool_init()
3719 spin_unlock_irqrestore(&port->pool_long->lock, flags); in mvpp2_swf_bm_pool_init()
3722 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); in mvpp2_swf_bm_pool_init()
3725 if (!port->pool_short) { in mvpp2_swf_bm_pool_init()
3726 port->pool_short = in mvpp2_swf_bm_pool_init()
3727 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_SHORT_POOL, in mvpp2_swf_bm_pool_init()
3730 if (!port->pool_short) in mvpp2_swf_bm_pool_init()
3733 spin_lock_irqsave(&port->pool_short->lock, flags); in mvpp2_swf_bm_pool_init()
3734 port->pool_short->port_map |= (1 << port->id); in mvpp2_swf_bm_pool_init()
3735 spin_unlock_irqrestore(&port->pool_short->lock, flags); in mvpp2_swf_bm_pool_init()
3738 mvpp2_rxq_short_pool_set(port, rxq, in mvpp2_swf_bm_pool_init()
3739 port->pool_short->id); in mvpp2_swf_bm_pool_init()
3747 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_bm_update_mtu() local
3748 struct mvpp2_bm_pool *port_pool = port->pool_long; in mvpp2_bm_update_mtu()
3753 mvpp2_bm_bufs_free(port->priv, port_pool); in mvpp2_bm_update_mtu()
3760 num = mvpp2_bm_bufs_add(port, port_pool, pkts_num); in mvpp2_bm_update_mtu()
3767 mvpp2_bm_pool_bufsize_set(port->priv, port_pool, in mvpp2_bm_update_mtu()
3774 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) in mvpp2_interrupts_enable() argument
3780 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_enable()
3784 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) in mvpp2_interrupts_disable() argument
3790 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_disable()
3797 struct mvpp2_port *port = arg; in mvpp2_interrupts_mask() local
3799 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); in mvpp2_interrupts_mask()
3805 struct mvpp2_port *port = arg; in mvpp2_interrupts_unmask() local
3807 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_MASK_REG(port->id), in mvpp2_interrupts_unmask()
3815 static void mvpp2_port_mii_set(struct mvpp2_port *port) in mvpp2_port_mii_set() argument
3819 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_mii_set()
3821 switch (port->phy_interface) { in mvpp2_port_mii_set()
3831 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_mii_set()
3834 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port) in mvpp2_port_fc_adv_enable() argument
3838 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_fc_adv_enable()
3840 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_fc_adv_enable()
3843 static void mvpp2_port_enable(struct mvpp2_port *port) in mvpp2_port_enable() argument
3847 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
3850 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
3853 static void mvpp2_port_disable(struct mvpp2_port *port) in mvpp2_port_disable() argument
3857 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
3859 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
3863 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) in mvpp2_port_periodic_xon_disable() argument
3867 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & in mvpp2_port_periodic_xon_disable()
3869 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_periodic_xon_disable()
3873 static void mvpp2_port_loopback_set(struct mvpp2_port *port) in mvpp2_port_loopback_set() argument
3877 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
3879 if (port->speed == 1000) in mvpp2_port_loopback_set()
3884 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) in mvpp2_port_loopback_set()
3889 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
3892 static void mvpp2_port_reset(struct mvpp2_port *port) in mvpp2_port_reset() argument
3896 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_port_reset()
3898 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_reset()
3900 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_port_reset()
3906 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) in mvpp2_gmac_max_rx_size_set() argument
3910 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
3912 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << in mvpp2_gmac_max_rx_size_set()
3914 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
3918 static void mvpp2_defaults_set(struct mvpp2_port *port) in mvpp2_defaults_set() argument
3923 if (port->flags & MVPP2_F_LOOPBACK) in mvpp2_defaults_set()
3924 mvpp2_port_loopback_set(port); in mvpp2_defaults_set()
3927 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
3931 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
3934 tx_port_num = mvpp2_egress_port(port); in mvpp2_defaults_set()
3935 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set()
3937 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); in mvpp2_defaults_set()
3941 ptxq = mvpp2_txq_phys(port->id, queue); in mvpp2_defaults_set()
3942 mvpp2_write(port->priv, in mvpp2_defaults_set()
3949 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, in mvpp2_defaults_set()
3950 port->priv->tclk / USEC_PER_SEC); in mvpp2_defaults_set()
3951 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); in mvpp2_defaults_set()
3955 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); in mvpp2_defaults_set()
3957 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_defaults_set()
3960 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), in mvpp2_defaults_set()
3966 queue = port->rxqs[lrxq]->id; in mvpp2_defaults_set()
3967 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_defaults_set()
3970 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
3974 mvpp2_interrupts_disable(port); in mvpp2_defaults_set()
3978 static void mvpp2_ingress_enable(struct mvpp2_port *port) in mvpp2_ingress_enable() argument
3984 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_enable()
3985 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_enable()
3987 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
3991 static void mvpp2_ingress_disable(struct mvpp2_port *port) in mvpp2_ingress_disable() argument
3997 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_disable()
3998 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_disable()
4000 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
4007 static void mvpp2_egress_enable(struct mvpp2_port *port) in mvpp2_egress_enable() argument
4011 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_enable()
4016 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_egress_enable()
4022 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable()
4023 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); in mvpp2_egress_enable()
4029 static void mvpp2_egress_disable(struct mvpp2_port *port) in mvpp2_egress_disable() argument
4033 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_disable()
4036 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable()
4037 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & in mvpp2_egress_disable()
4040 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, in mvpp2_egress_disable()
4047 netdev_warn(port->dev, in mvpp2_egress_disable()
4058 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); in mvpp2_egress_disable()
4066 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) in mvpp2_rxq_received() argument
4068 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); in mvpp2_rxq_received()
4077 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, in mvpp2_rxq_status_update() argument
4085 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); in mvpp2_rxq_status_update()
4100 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, in mvpp2_rxq_offset_set() argument
4108 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_offset_set()
4115 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()
4132 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port, in mvpp2_txq_pend_desc_num_get() argument
4137 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_pend_desc_num_get()
4138 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_pend_desc_num_get()
4154 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) in mvpp2_aggr_txq_pend_desc_add() argument
4157 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending); in mvpp2_aggr_txq_pend_desc_add()
4285 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, in mvpp2_txq_sent_desc_proc() argument
4291 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id)); in mvpp2_txq_sent_desc_proc()
4299 struct mvpp2_port *port = arg; in mvpp2_txq_sent_counter_clear() local
4303 int id = port->txqs[queue]->id; in mvpp2_txq_sent_counter_clear()
4305 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id)); in mvpp2_txq_sent_counter_clear()
4310 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) in mvpp2_txp_max_tx_size_set() argument
4315 mtu = port->pkt_size * 8; in mvpp2_txp_max_tx_size_set()
4323 tx_port_num = mvpp2_egress_port(port); in mvpp2_txp_max_tx_size_set()
4324 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set()
4327 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); in mvpp2_txp_max_tx_size_set()
4330 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); in mvpp2_txp_max_tx_size_set()
4333 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); in mvpp2_txp_max_tx_size_set()
4339 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_txp_max_tx_size_set()
4343 val = mvpp2_read(port->priv, in mvpp2_txp_max_tx_size_set()
4351 mvpp2_write(port->priv, in mvpp2_txp_max_tx_size_set()
4361 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, in mvpp2_rx_pkts_coal_set() argument
4367 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rx_pkts_coal_set()
4368 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val); in mvpp2_rx_pkts_coal_set()
4374 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, in mvpp2_rx_time_coal_set() argument
4379 val = (port->priv->tclk / USEC_PER_SEC) * usec; in mvpp2_rx_time_coal_set()
4380 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); in mvpp2_rx_time_coal_set()
4388 struct mvpp2_port *port = arg; in mvpp2_tx_done_pkts_coal_set() local
4393 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_tx_done_pkts_coal_set()
4397 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_tx_done_pkts_coal_set()
4398 mvpp2_write(port->priv, MVPP2_TXQ_THRESH_REG, val); in mvpp2_tx_done_pkts_coal_set()
4403 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, in mvpp2_txq_bufs_free() argument
4419 dma_unmap_single(port->dev->dev.parent, tx_desc->buf_phys_addr, in mvpp2_txq_bufs_free()
4425 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, in mvpp2_get_rx_queue() argument
4430 return port->rxqs[queue]; in mvpp2_get_rx_queue()
4433 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, in mvpp2_get_tx_queue() argument
4438 return port->txqs[queue]; in mvpp2_get_tx_queue()
4442 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, in mvpp2_txq_done() argument
4445 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); in mvpp2_txq_done()
4449 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); in mvpp2_txq_done()
4451 tx_done = mvpp2_txq_sent_desc_proc(port, txq); in mvpp2_txq_done()
4454 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); in mvpp2_txq_done()
4498 static int mvpp2_rxq_init(struct mvpp2_port *port, in mvpp2_rxq_init() argument
4502 rxq->size = port->rx_ring_size; in mvpp2_rxq_init()
4505 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, in mvpp2_rxq_init()
4517 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_init()
4520 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_init()
4521 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_phys); in mvpp2_rxq_init()
4522 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); in mvpp2_rxq_init()
4523 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0); in mvpp2_rxq_init()
4526 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); in mvpp2_rxq_init()
4529 mvpp2_rx_pkts_coal_set(port, rxq, rxq->pkts_coal); in mvpp2_rxq_init()
4530 mvpp2_rx_time_coal_set(port, rxq, rxq->time_coal); in mvpp2_rxq_init()
4533 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); in mvpp2_rxq_init()
4539 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, in mvpp2_rxq_drop_pkts() argument
4544 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rxq_drop_pkts()
4552 mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr, in mvpp2_rxq_drop_pkts()
4555 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); in mvpp2_rxq_drop_pkts()
4559 static void mvpp2_rxq_deinit(struct mvpp2_port *port, in mvpp2_rxq_deinit() argument
4562 mvpp2_rxq_drop_pkts(port, rxq); in mvpp2_rxq_deinit()
4565 dma_free_coherent(port->dev->dev.parent, in mvpp2_rxq_deinit()
4578 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_deinit()
4579 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_deinit()
4580 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0); in mvpp2_rxq_deinit()
4581 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0); in mvpp2_rxq_deinit()
4585 static int mvpp2_txq_init(struct mvpp2_port *port, in mvpp2_txq_init() argument
4592 txq->size = port->tx_ring_size; in mvpp2_txq_init()
4595 txq->descs = dma_alloc_coherent(port->dev->dev.parent, in mvpp2_txq_init()
4608 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_init()
4609 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_phys); in mvpp2_txq_init()
4610 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size & in mvpp2_txq_init()
4612 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0); in mvpp2_txq_init()
4613 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG, in mvpp2_txq_init()
4615 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_init()
4617 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val); in mvpp2_txq_init()
4625 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + in mvpp2_txq_init()
4628 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, in mvpp2_txq_init()
4633 tx_port_num = mvpp2_egress_port(port); in mvpp2_txq_init()
4634 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
4636 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); in mvpp2_txq_init()
4640 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); in mvpp2_txq_init()
4643 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), in mvpp2_txq_init()
4653 dma_free_coherent(port->dev->dev.parent, in mvpp2_txq_init()
4669 static void mvpp2_txq_deinit(struct mvpp2_port *port, in mvpp2_txq_deinit() argument
4681 dma_free_coherent(port->dev->dev.parent, in mvpp2_txq_deinit()
4691 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); in mvpp2_txq_deinit()
4694 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_deinit()
4695 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0); in mvpp2_txq_deinit()
4696 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0); in mvpp2_txq_deinit()
4700 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) in mvpp2_txq_clean() argument
4706 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_clean()
4707 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG); in mvpp2_txq_clean()
4709 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4717 netdev_warn(port->dev, in mvpp2_txq_clean()
4719 port->id, txq->log_id); in mvpp2_txq_clean()
4725 pending = mvpp2_txq_pend_desc_num_get(port, txq); in mvpp2_txq_clean()
4729 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4735 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); in mvpp2_txq_clean()
4745 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) in mvpp2_cleanup_txqs() argument
4751 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); in mvpp2_cleanup_txqs()
4754 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
4755 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4758 txq = port->txqs[queue]; in mvpp2_cleanup_txqs()
4759 mvpp2_txq_clean(port, txq); in mvpp2_cleanup_txqs()
4760 mvpp2_txq_deinit(port, txq); in mvpp2_cleanup_txqs()
4763 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); in mvpp2_cleanup_txqs()
4765 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
4766 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4770 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) in mvpp2_cleanup_rxqs() argument
4775 mvpp2_rxq_deinit(port, port->rxqs[queue]); in mvpp2_cleanup_rxqs()
4779 static int mvpp2_setup_rxqs(struct mvpp2_port *port) in mvpp2_setup_rxqs() argument
4784 err = mvpp2_rxq_init(port, port->rxqs[queue]); in mvpp2_setup_rxqs()
4791 mvpp2_cleanup_rxqs(port); in mvpp2_setup_rxqs()
4796 static int mvpp2_setup_txqs(struct mvpp2_port *port) in mvpp2_setup_txqs() argument
4802 txq = port->txqs[queue]; in mvpp2_setup_txqs()
4803 err = mvpp2_txq_init(port, txq); in mvpp2_setup_txqs()
4808 on_each_cpu(mvpp2_tx_done_pkts_coal_set, port, 1); in mvpp2_setup_txqs()
4809 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); in mvpp2_setup_txqs()
4813 mvpp2_cleanup_txqs(port); in mvpp2_setup_txqs()
4820 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; in mvpp2_isr() local
4822 mvpp2_interrupts_disable(port); in mvpp2_isr()
4824 napi_schedule(&port->napi); in mvpp2_isr()
4832 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_link_event() local
4833 struct phy_device *phydev = port->phy_dev; in mvpp2_link_event()
4838 if ((port->speed != phydev->speed) || in mvpp2_link_event()
4839 (port->duplex != phydev->duplex)) { in mvpp2_link_event()
4842 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4857 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4859 port->duplex = phydev->duplex; in mvpp2_link_event()
4860 port->speed = phydev->speed; in mvpp2_link_event()
4864 if (phydev->link != port->link) { in mvpp2_link_event()
4866 port->duplex = -1; in mvpp2_link_event()
4867 port->speed = 0; in mvpp2_link_event()
4870 port->link = phydev->link; in mvpp2_link_event()
4876 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4879 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4880 mvpp2_egress_enable(port); in mvpp2_link_event()
4881 mvpp2_ingress_enable(port); in mvpp2_link_event()
4883 mvpp2_ingress_disable(port); in mvpp2_link_event()
4884 mvpp2_egress_disable(port); in mvpp2_link_event()
4893 static void mvpp2_rx_error(struct mvpp2_port *port, in mvpp2_rx_error() argument
4900 netdev_err(port->dev, "bad rx status %08x (crc error), size=%d\n", in mvpp2_rx_error()
4904 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%d\n", in mvpp2_rx_error()
4908 netdev_err(port->dev, "bad rx status %08x (resource error), size=%d\n", in mvpp2_rx_error()
4915 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, in mvpp2_rx_csum() argument
4933 static int mvpp2_rx_refill(struct mvpp2_port *port, in mvpp2_rx_refill() argument
4945 skb = mvpp2_skb_alloc(port, bm_pool, &phys_addr, GFP_ATOMIC); in mvpp2_rx_refill()
4949 mvpp2_pool_refill(port, bm, (u32)phys_addr, (u32)skb); in mvpp2_rx_refill()
4955 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) in mvpp2_skb_tx_csum() argument
4985 static void mvpp2_buff_hdr_rx(struct mvpp2_port *port, in mvpp2_buff_hdr_rx() argument
5013 mvpp2_bm_pool_mc_put(port, pool_id, buff_phys_addr, in mvpp2_buff_hdr_rx()
5023 static int mvpp2_rx(struct mvpp2_port *port, int rx_todo, in mvpp2_rx() argument
5026 struct net_device *dev = port->dev; in mvpp2_rx()
5032 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rx()
5050 bm_pool = &port->priv->bm_pools[pool]; in mvpp2_rx()
5053 mvpp2_buff_hdr_rx(port, rx_desc); in mvpp2_rx()
5064 mvpp2_rx_error(port, rx_desc); in mvpp2_rx()
5065 mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr, in mvpp2_rx()
5079 mvpp2_rx_csum(port, rx_status, skb); in mvpp2_rx()
5081 napi_gro_receive(&port->napi, skb); in mvpp2_rx()
5083 err = mvpp2_rx_refill(port, bm_pool, bm, 0); in mvpp2_rx()
5085 netdev_err(port->dev, "failed to refill BM pools\n"); in mvpp2_rx()
5091 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); in mvpp2_rx()
5101 mvpp2_rxq_status_update(port, rxq->id, rx_todo, rx_filled); in mvpp2_rx()
5116 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, in mvpp2_tx_frag_process() argument
5133 buf_phys_addr = dma_map_single(port->dev->dev.parent, addr, in mvpp2_tx_frag_process()
5136 if (dma_mapping_error(port->dev->dev.parent, buf_phys_addr)) { in mvpp2_tx_frag_process()
5163 tx_desc_unmap_put(port->dev->dev.parent, txq, tx_desc); in mvpp2_tx_frag_process()
5172 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_tx() local
5182 txq = port->txqs[txq_id]; in mvpp2_tx()
5184 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; in mvpp2_tx()
5189 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) || in mvpp2_tx()
5190 mvpp2_txq_reserved_desc_num_proc(port->priv, txq, in mvpp2_tx()
5211 tx_cmd = mvpp2_skb_tx_csum(port, skb); in mvpp2_tx()
5225 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { in mvpp2_tx()
5226 tx_desc_unmap_put(port->dev->dev.parent, txq, tx_desc); in mvpp2_tx()
5238 mvpp2_aggr_txq_pend_desc_add(port, frags); in mvpp2_tx()
5247 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); in mvpp2_tx()
5273 struct mvpp2_port *port = arg; in mvpp2_txq_done_percpu() local
5286 cause_rx_tx = mvpp2_read(port->priv, in mvpp2_txq_done_percpu()
5287 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); in mvpp2_txq_done_percpu()
5292 mvpp2_cause_error(port->dev, cause_misc); in mvpp2_txq_done_percpu()
5295 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); in mvpp2_txq_done_percpu()
5296 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_CAUSE_REG(port->id), in mvpp2_txq_done_percpu()
5302 struct mvpp2_tx_queue *txq = mvpp2_get_tx_queue(port, cause_tx); in mvpp2_txq_done_percpu()
5306 mvpp2_txq_done(port, txq, txq_pcpu); in mvpp2_txq_done_percpu()
5314 struct mvpp2_port *port = netdev_priv(napi->dev); in mvpp2_poll() local
5316 on_each_cpu(mvpp2_txq_done_percpu, port, 1); in mvpp2_poll()
5318 cause_rx_tx = mvpp2_read(port->priv, in mvpp2_poll()
5319 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); in mvpp2_poll()
5323 cause_rx |= port->pending_cause_rx; in mvpp2_poll()
5328 rxq = mvpp2_get_rx_queue(port, cause_rx); in mvpp2_poll()
5332 count = mvpp2_rx(port, budget, rxq); in mvpp2_poll()
5348 mvpp2_interrupts_enable(port); in mvpp2_poll()
5350 port->pending_cause_rx = cause_rx; in mvpp2_poll()
5355 static void mvpp2_start_dev(struct mvpp2_port *port) in mvpp2_start_dev() argument
5357 mvpp2_gmac_max_rx_size_set(port); in mvpp2_start_dev()
5358 mvpp2_txp_max_tx_size_set(port); in mvpp2_start_dev()
5360 napi_enable(&port->napi); in mvpp2_start_dev()
5363 mvpp2_interrupts_enable(port); in mvpp2_start_dev()
5365 mvpp2_port_enable(port); in mvpp2_start_dev()
5366 phy_start(port->phy_dev); in mvpp2_start_dev()
5367 netif_tx_start_all_queues(port->dev); in mvpp2_start_dev()
5371 static void mvpp2_stop_dev(struct mvpp2_port *port) in mvpp2_stop_dev() argument
5374 mvpp2_ingress_disable(port); in mvpp2_stop_dev()
5379 mvpp2_interrupts_disable(port); in mvpp2_stop_dev()
5381 napi_disable(&port->napi); in mvpp2_stop_dev()
5383 netif_carrier_off(port->dev); in mvpp2_stop_dev()
5384 netif_tx_stop_all_queues(port->dev); in mvpp2_stop_dev()
5386 mvpp2_egress_disable(port); in mvpp2_stop_dev()
5387 mvpp2_port_disable(port); in mvpp2_stop_dev()
5388 phy_stop(port->phy_dev); in mvpp2_stop_dev()
5448 static void mvpp2_get_mac_address(struct mvpp2_port *port, unsigned char *addr) in mvpp2_get_mac_address() argument
5452 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_get_mac_address()
5453 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); in mvpp2_get_mac_address()
5454 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); in mvpp2_get_mac_address()
5463 static int mvpp2_phy_connect(struct mvpp2_port *port) in mvpp2_phy_connect() argument
5467 phy_dev = of_phy_connect(port->dev, port->phy_node, mvpp2_link_event, 0, in mvpp2_phy_connect()
5468 port->phy_interface); in mvpp2_phy_connect()
5470 netdev_err(port->dev, "cannot connect to phy\n"); in mvpp2_phy_connect()
5476 port->phy_dev = phy_dev; in mvpp2_phy_connect()
5477 port->link = 0; in mvpp2_phy_connect()
5478 port->duplex = 0; in mvpp2_phy_connect()
5479 port->speed = 0; in mvpp2_phy_connect()
5484 static void mvpp2_phy_disconnect(struct mvpp2_port *port) in mvpp2_phy_disconnect() argument
5486 phy_disconnect(port->phy_dev); in mvpp2_phy_disconnect()
5487 port->phy_dev = NULL; in mvpp2_phy_disconnect()
5492 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_open() local
5497 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true); in mvpp2_open()
5502 err = mvpp2_prs_mac_da_accept(port->priv, port->id, in mvpp2_open()
5508 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); in mvpp2_open()
5513 err = mvpp2_prs_def_flow(port); in mvpp2_open()
5520 err = mvpp2_setup_rxqs(port); in mvpp2_open()
5522 netdev_err(port->dev, "cannot allocate Rx queues\n"); in mvpp2_open()
5526 err = mvpp2_setup_txqs(port); in mvpp2_open()
5528 netdev_err(port->dev, "cannot allocate Tx queues\n"); in mvpp2_open()
5532 err = request_irq(port->irq, mvpp2_isr, 0, dev->name, port); in mvpp2_open()
5534 netdev_err(port->dev, "cannot request IRQ %d\n", port->irq); in mvpp2_open()
5539 netif_carrier_off(port->dev); in mvpp2_open()
5541 err = mvpp2_phy_connect(port); in mvpp2_open()
5546 on_each_cpu(mvpp2_interrupts_unmask, port, 1); in mvpp2_open()
5548 mvpp2_start_dev(port); in mvpp2_open()
5553 free_irq(port->irq, port); in mvpp2_open()
5555 mvpp2_cleanup_txqs(port); in mvpp2_open()
5557 mvpp2_cleanup_rxqs(port); in mvpp2_open()
5563 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_stop() local
5565 mvpp2_stop_dev(port); in mvpp2_stop()
5566 mvpp2_phy_disconnect(port); in mvpp2_stop()
5569 on_each_cpu(mvpp2_interrupts_mask, port, 1); in mvpp2_stop()
5571 free_irq(port->irq, port); in mvpp2_stop()
5572 mvpp2_cleanup_rxqs(port); in mvpp2_stop()
5573 mvpp2_cleanup_txqs(port); in mvpp2_stop()
5580 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_set_rx_mode() local
5581 struct mvpp2 *priv = port->priv; in mvpp2_set_rx_mode()
5583 int id = port->id; in mvpp2_set_rx_mode()
5601 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_set_mac_address() local
5620 mvpp2_stop_dev(port); in mvpp2_set_mac_address()
5631 mvpp2_start_dev(port); in mvpp2_set_mac_address()
5632 mvpp2_egress_enable(port); in mvpp2_set_mac_address()
5633 mvpp2_ingress_enable(port); in mvpp2_set_mac_address()
5643 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_change_mtu() local
5655 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); in mvpp2_change_mtu()
5665 mvpp2_stop_dev(port); in mvpp2_change_mtu()
5669 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); in mvpp2_change_mtu()
5679 mvpp2_start_dev(port); in mvpp2_change_mtu()
5680 mvpp2_egress_enable(port); in mvpp2_change_mtu()
5681 mvpp2_ingress_enable(port); in mvpp2_change_mtu()
5693 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_get_stats64() local
5704 cpu_stats = per_cpu_ptr(port->stats, cpu); in mvpp2_get_stats64()
5728 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ioctl() local
5731 if (!port->phy_dev) in mvpp2_ioctl()
5734 ret = phy_mii_ioctl(port->phy_dev, ifr, cmd); in mvpp2_ioctl()
5747 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_settings() local
5749 if (!port->phy_dev) in mvpp2_ethtool_get_settings()
5751 return phy_ethtool_gset(port->phy_dev, cmd); in mvpp2_ethtool_get_settings()
5758 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_settings() local
5760 if (!port->phy_dev) in mvpp2_ethtool_set_settings()
5762 return phy_ethtool_sset(port->phy_dev, cmd); in mvpp2_ethtool_set_settings()
5769 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_coalesce() local
5773 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_ethtool_set_coalesce()
5777 mvpp2_rx_pkts_coal_set(port, rxq, rxq->pkts_coal); in mvpp2_ethtool_set_coalesce()
5778 mvpp2_rx_time_coal_set(port, rxq, rxq->time_coal); in mvpp2_ethtool_set_coalesce()
5782 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_ethtool_set_coalesce()
5787 on_each_cpu(mvpp2_tx_done_pkts_coal_set, port, 1); in mvpp2_ethtool_set_coalesce()
5795 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_coalesce() local
5797 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; in mvpp2_ethtool_get_coalesce()
5798 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; in mvpp2_ethtool_get_coalesce()
5799 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; in mvpp2_ethtool_get_coalesce()
5817 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_ringparam() local
5821 ring->rx_pending = port->rx_ring_size; in mvpp2_ethtool_get_ringparam()
5822 ring->tx_pending = port->tx_ring_size; in mvpp2_ethtool_get_ringparam()
5828 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_ringparam() local
5829 u16 prev_rx_ring_size = port->rx_ring_size; in mvpp2_ethtool_set_ringparam()
5830 u16 prev_tx_ring_size = port->tx_ring_size; in mvpp2_ethtool_set_ringparam()
5838 port->rx_ring_size = ring->rx_pending; in mvpp2_ethtool_set_ringparam()
5839 port->tx_ring_size = ring->tx_pending; in mvpp2_ethtool_set_ringparam()
5846 mvpp2_stop_dev(port); in mvpp2_ethtool_set_ringparam()
5847 mvpp2_cleanup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5848 mvpp2_cleanup_txqs(port); in mvpp2_ethtool_set_ringparam()
5850 port->rx_ring_size = ring->rx_pending; in mvpp2_ethtool_set_ringparam()
5851 port->tx_ring_size = ring->tx_pending; in mvpp2_ethtool_set_ringparam()
5853 err = mvpp2_setup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5856 port->rx_ring_size = prev_rx_ring_size; in mvpp2_ethtool_set_ringparam()
5858 err = mvpp2_setup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5862 err = mvpp2_setup_txqs(port); in mvpp2_ethtool_set_ringparam()
5865 port->tx_ring_size = prev_tx_ring_size; in mvpp2_ethtool_set_ringparam()
5867 err = mvpp2_setup_txqs(port); in mvpp2_ethtool_set_ringparam()
5872 mvpp2_start_dev(port); in mvpp2_ethtool_set_ringparam()
5873 mvpp2_egress_enable(port); in mvpp2_ethtool_set_ringparam()
5874 mvpp2_ingress_enable(port); in mvpp2_ethtool_set_ringparam()
5879 mvpp2_cleanup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5911 static void mvpp2_port_power_up(struct mvpp2_port *port) in mvpp2_port_power_up() argument
5913 mvpp2_port_mii_set(port); in mvpp2_port_power_up()
5914 mvpp2_port_periodic_xon_disable(port); in mvpp2_port_power_up()
5915 mvpp2_port_fc_adv_enable(port); in mvpp2_port_power_up()
5916 mvpp2_port_reset(port); in mvpp2_port_power_up()
5920 static int mvpp2_port_init(struct mvpp2_port *port) in mvpp2_port_init() argument
5922 struct device *dev = port->dev->dev.parent; in mvpp2_port_init()
5923 struct mvpp2 *priv = port->priv; in mvpp2_port_init()
5927 if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM) in mvpp2_port_init()
5931 mvpp2_egress_disable(port); in mvpp2_port_init()
5932 mvpp2_port_disable(port); in mvpp2_port_init()
5934 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs), in mvpp2_port_init()
5936 if (!port->txqs) in mvpp2_port_init()
5943 int queue_phy_id = mvpp2_txq_phys(port->id, queue); in mvpp2_port_init()
5964 port->txqs[queue] = txq; in mvpp2_port_init()
5967 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs), in mvpp2_port_init()
5969 if (!port->rxqs) { in mvpp2_port_init()
5983 rxq->id = port->first_rxq + queue; in mvpp2_port_init()
5984 rxq->port = port->id; in mvpp2_port_init()
5987 port->rxqs[queue] = rxq; in mvpp2_port_init()
5991 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), rxq_number); in mvpp2_port_init()
5995 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_port_init()
5997 rxq->size = port->rx_ring_size; in mvpp2_port_init()
6002 mvpp2_ingress_disable(port); in mvpp2_port_init()
6005 mvpp2_defaults_set(port); in mvpp2_port_init()
6008 mvpp2_cls_oversize_rxq_set(port); in mvpp2_port_init()
6009 mvpp2_cls_port_config(port); in mvpp2_port_init()
6012 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); in mvpp2_port_init()
6015 err = mvpp2_swf_bm_pool_init(port); in mvpp2_port_init()
6023 if (!port->txqs[queue]) in mvpp2_port_init()
6025 free_percpu(port->txqs[queue]->pcpu); in mvpp2_port_init()
6037 struct mvpp2_port *port; in mvpp2_port_probe() local
6079 port = netdev_priv(dev); in mvpp2_port_probe()
6081 port->irq = irq_of_parse_and_map(port_node, 0); in mvpp2_port_probe()
6082 if (port->irq <= 0) { in mvpp2_port_probe()
6088 port->flags |= MVPP2_F_LOOPBACK; in mvpp2_port_probe()
6090 port->priv = priv; in mvpp2_port_probe()
6091 port->id = id; in mvpp2_port_probe()
6092 port->first_rxq = *next_first_rxq; in mvpp2_port_probe()
6093 port->phy_node = phy_node; in mvpp2_port_probe()
6094 port->phy_interface = phy_mode; in mvpp2_port_probe()
6098 port->base = devm_ioremap_resource(&pdev->dev, res); in mvpp2_port_probe()
6099 if (IS_ERR(port->base)) { in mvpp2_port_probe()
6100 err = PTR_ERR(port->base); in mvpp2_port_probe()
6105 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); in mvpp2_port_probe()
6106 if (!port->stats) { in mvpp2_port_probe()
6116 mvpp2_get_mac_address(port, hw_mac_addr); in mvpp2_port_probe()
6126 port->tx_ring_size = MVPP2_MAX_TXD; in mvpp2_port_probe()
6127 port->rx_ring_size = MVPP2_MAX_RXD; in mvpp2_port_probe()
6128 port->dev = dev; in mvpp2_port_probe()
6131 err = mvpp2_port_init(port); in mvpp2_port_probe()
6136 mvpp2_port_power_up(port); in mvpp2_port_probe()
6138 netif_napi_add(dev, &port->napi, mvpp2_poll, NAPI_POLL_WEIGHT); in mvpp2_port_probe()
6153 priv->port_list[id] = port; in mvpp2_port_probe()
6158 free_percpu(port->txqs[i]->pcpu); in mvpp2_port_probe()
6160 free_percpu(port->stats); in mvpp2_port_probe()
6162 irq_dispose_mapping(port->irq); in mvpp2_port_probe()
6169 static void mvpp2_port_remove(struct mvpp2_port *port) in mvpp2_port_remove() argument
6173 unregister_netdev(port->dev); in mvpp2_port_remove()
6174 free_percpu(port->stats); in mvpp2_port_remove()
6176 free_percpu(port->txqs[i]->pcpu); in mvpp2_port_remove()
6177 irq_dispose_mapping(port->irq); in mvpp2_port_remove()
6178 free_netdev(port->dev); in mvpp2_port_remove()
6217 int port; in mvpp2_rx_fifo_init() local
6219 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_rx_fifo_init()
6220 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
6222 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()