Lines Matching refs:pe
989 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_write() argument
993 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
997 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; in mvpp2_prs_hw_write()
1000 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1002 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); in mvpp2_prs_hw_write()
1005 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1007 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1013 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_read() argument
1017 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_read()
1021 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1023 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, in mvpp2_prs_hw_read()
1025 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) in mvpp2_prs_hw_read()
1029 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1032 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1034 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1064 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) in mvpp2_prs_tcam_lu_set() argument
1068 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu; in mvpp2_prs_tcam_lu_set()
1069 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK; in mvpp2_prs_tcam_lu_set()
1073 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_set() argument
1079 pe->tcam.byte[enable_off] &= ~(1 << port); in mvpp2_prs_tcam_port_set()
1081 pe->tcam.byte[enable_off] |= 1 << port; in mvpp2_prs_tcam_port_set()
1085 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_map_set() argument
1091 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0; in mvpp2_prs_tcam_port_map_set()
1092 pe->tcam.byte[enable_off] &= ~port_mask; in mvpp2_prs_tcam_port_map_set()
1093 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_set()
1097 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_port_map_get() argument
1101 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_get()
1105 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_set() argument
1109 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte; in mvpp2_prs_tcam_data_byte_set()
1110 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable; in mvpp2_prs_tcam_data_byte_set()
1114 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_get() argument
1118 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)]; in mvpp2_prs_tcam_data_byte_get()
1119 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)]; in mvpp2_prs_tcam_data_byte_get()
1123 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs, in mvpp2_prs_tcam_data_cmp() argument
1129 tcam_data = (8 << pe->tcam.byte[off + 1]) | pe->tcam.byte[off]; in mvpp2_prs_tcam_data_cmp()
1136 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_ai_update() argument
1147 pe->tcam.byte[ai_idx] |= 1 << i; in mvpp2_prs_tcam_ai_update()
1149 pe->tcam.byte[ai_idx] &= ~(1 << i); in mvpp2_prs_tcam_ai_update()
1152 pe->tcam.byte[MVPP2_PRS_TCAM_EN_OFFS(ai_idx)] |= enable; in mvpp2_prs_tcam_ai_update()
1156 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_ai_get() argument
1158 return pe->tcam.byte[MVPP2_PRS_TCAM_AI_BYTE]; in mvpp2_prs_tcam_ai_get()
1162 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_etype() argument
1165 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); in mvpp2_prs_match_etype()
1166 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); in mvpp2_prs_match_etype()
1170 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_set() argument
1173 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8)); in mvpp2_prs_sram_bits_set()
1177 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_clear() argument
1180 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8)); in mvpp2_prs_sram_bits_clear()
1184 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ri_update() argument
1196 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1); in mvpp2_prs_sram_ri_update()
1198 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1); in mvpp2_prs_sram_ri_update()
1200 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ri_update()
1205 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ri_get() argument
1207 return pe->sram.word[MVPP2_PRS_SRAM_RI_WORD]; in mvpp2_prs_sram_ri_get()
1211 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ai_update() argument
1223 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1); in mvpp2_prs_sram_ai_update()
1225 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1); in mvpp2_prs_sram_ai_update()
1227 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ai_update()
1232 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ai_get() argument
1239 bits = (pe->sram.byte[ai_off] >> ai_shift) | in mvpp2_prs_sram_ai_get()
1240 (pe->sram.byte[ai_en_off] << (8 - ai_shift)); in mvpp2_prs_sram_ai_get()
1248 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_next_lu_set() argument
1253 mvpp2_prs_sram_bits_clear(pe, sram_next_off, in mvpp2_prs_sram_next_lu_set()
1255 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); in mvpp2_prs_sram_next_lu_set()
1261 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, in mvpp2_prs_sram_shift_set() argument
1266 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
1269 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
1273 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = in mvpp2_prs_sram_shift_set()
1277 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, in mvpp2_prs_sram_shift_set()
1279 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); in mvpp2_prs_sram_shift_set()
1282 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_shift_set()
1288 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_offset_set() argument
1294 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
1297 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
1301 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
1303 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset); in mvpp2_prs_sram_offset_set()
1304 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1307 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1312 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, in mvpp2_prs_sram_offset_set()
1314 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); in mvpp2_prs_sram_offset_set()
1317 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
1319 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op); in mvpp2_prs_sram_offset_set()
1321 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1326 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1331 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_offset_set()
1337 struct mvpp2_prs_entry *pe; in mvpp2_prs_flow_find() local
1340 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_flow_find()
1341 if (!pe) in mvpp2_prs_flow_find()
1343 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_flow_find()
1353 pe->index = tid; in mvpp2_prs_flow_find()
1354 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_flow_find()
1355 bits = mvpp2_prs_sram_ai_get(pe); in mvpp2_prs_flow_find()
1359 return pe; in mvpp2_prs_flow_find()
1361 kfree(pe); in mvpp2_prs_flow_find()
1389 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_drop_all_set() local
1393 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
1394 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_drop_all_set()
1397 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_drop_all_set()
1398 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
1399 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
1402 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_drop_all_set()
1405 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_drop_all_set()
1406 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_drop_all_set()
1409 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
1412 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_drop_all_set()
1416 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
1418 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_drop_all_set()
1424 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_promisc_set() local
1430 pe.index = MVPP2_PE_MAC_PROMISCUOUS; in mvpp2_prs_mac_promisc_set()
1431 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_promisc_set()
1434 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_promisc_set()
1435 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
1436 pe.index = MVPP2_PE_MAC_PROMISCUOUS; in mvpp2_prs_mac_promisc_set()
1439 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_promisc_set()
1442 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST, in mvpp2_prs_mac_promisc_set()
1446 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_promisc_set()
1450 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_promisc_set()
1453 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
1457 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
1459 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_promisc_set()
1466 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_multi_set() local
1476 pe.index = index; in mvpp2_prs_mac_multi_set()
1477 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_multi_set()
1480 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_multi_set()
1481 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_multi_set()
1482 pe.index = index; in mvpp2_prs_mac_multi_set()
1485 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_multi_set()
1488 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST, in mvpp2_prs_mac_multi_set()
1492 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff); in mvpp2_prs_mac_multi_set()
1495 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_multi_set()
1499 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_multi_set()
1502 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_multi_set()
1506 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_multi_set()
1508 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_multi_set()
1515 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_set() local
1528 pe.index = tid; in mvpp2_prs_dsa_tag_set()
1529 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_dsa_tag_set()
1532 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_dsa_tag_set()
1533 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
1534 pe.index = tid; in mvpp2_prs_dsa_tag_set()
1537 mvpp2_prs_sram_shift_set(&pe, shift, in mvpp2_prs_dsa_tag_set()
1541 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
1545 mvpp2_prs_tcam_data_byte_set(&pe, 0, in mvpp2_prs_dsa_tag_set()
1549 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_set()
1552 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_tag_set()
1555 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_set()
1557 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_set()
1561 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_dsa_tag_set()
1565 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_set()
1567 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_set()
1574 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_ethertype_set() local
1591 pe.index = tid; in mvpp2_prs_dsa_tag_ethertype_set()
1592 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_dsa_tag_ethertype_set()
1595 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_dsa_tag_ethertype_set()
1596 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
1597 pe.index = tid; in mvpp2_prs_dsa_tag_ethertype_set()
1600 mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA); in mvpp2_prs_dsa_tag_ethertype_set()
1601 mvpp2_prs_match_etype(&pe, 2, 0); in mvpp2_prs_dsa_tag_ethertype_set()
1603 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK, in mvpp2_prs_dsa_tag_ethertype_set()
1606 mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift, in mvpp2_prs_dsa_tag_ethertype_set()
1610 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
1614 mvpp2_prs_tcam_data_byte_set(&pe, in mvpp2_prs_dsa_tag_ethertype_set()
1619 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_ethertype_set()
1622 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_tag_ethertype_set()
1625 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_ethertype_set()
1627 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_ethertype_set()
1630 mvpp2_prs_tcam_port_map_set(&pe, port_mask); in mvpp2_prs_dsa_tag_ethertype_set()
1634 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_ethertype_set()
1636 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_ethertype_set()
1643 struct mvpp2_prs_entry *pe; in mvpp2_prs_vlan_find() local
1646 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_vlan_find()
1647 if (!pe) in mvpp2_prs_vlan_find()
1649 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_find()
1661 pe->index = tid; in mvpp2_prs_vlan_find()
1663 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_vlan_find()
1664 match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid)); in mvpp2_prs_vlan_find()
1669 ri_bits = mvpp2_prs_sram_ri_get(pe); in mvpp2_prs_vlan_find()
1673 ai_bits = mvpp2_prs_tcam_ai_get(pe); in mvpp2_prs_vlan_find()
1682 return pe; in mvpp2_prs_vlan_find()
1684 kfree(pe); in mvpp2_prs_vlan_find()
1693 struct mvpp2_prs_entry *pe; in mvpp2_prs_vlan_add() local
1697 pe = mvpp2_prs_vlan_find(priv, tpid, ai); in mvpp2_prs_vlan_add()
1699 if (!pe) { in mvpp2_prs_vlan_add()
1706 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_vlan_add()
1707 if (!pe) in mvpp2_prs_vlan_add()
1719 pe->index = tid_aux; in mvpp2_prs_vlan_add()
1720 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_vlan_add()
1721 ri_bits = mvpp2_prs_sram_ri_get(pe); in mvpp2_prs_vlan_add()
1732 memset(pe, 0 , sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_vlan_add()
1733 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
1734 pe->index = tid; in mvpp2_prs_vlan_add()
1736 mvpp2_prs_match_etype(pe, 0, tpid); in mvpp2_prs_vlan_add()
1738 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_add()
1740 mvpp2_prs_sram_shift_set(pe, MVPP2_VLAN_TAG_LEN, in mvpp2_prs_vlan_add()
1743 mvpp2_prs_sram_ai_update(pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
1746 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_SINGLE, in mvpp2_prs_vlan_add()
1750 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_TRIPLE, in mvpp2_prs_vlan_add()
1753 mvpp2_prs_tcam_ai_update(pe, ai, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
1755 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
1758 mvpp2_prs_tcam_port_map_set(pe, port_map); in mvpp2_prs_vlan_add()
1760 mvpp2_prs_hw_write(priv, pe); in mvpp2_prs_vlan_add()
1763 kfree(pe); in mvpp2_prs_vlan_add()
1786 struct mvpp2_prs_entry *pe; in mvpp2_prs_double_vlan_find() local
1789 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_double_vlan_find()
1790 if (!pe) in mvpp2_prs_double_vlan_find()
1792 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_find()
1804 pe->index = tid; in mvpp2_prs_double_vlan_find()
1805 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_double_vlan_find()
1807 match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid1)) in mvpp2_prs_double_vlan_find()
1808 && mvpp2_prs_tcam_data_cmp(pe, 4, swab16(tpid2)); in mvpp2_prs_double_vlan_find()
1813 ri_mask = mvpp2_prs_sram_ri_get(pe) & MVPP2_PRS_RI_VLAN_MASK; in mvpp2_prs_double_vlan_find()
1815 return pe; in mvpp2_prs_double_vlan_find()
1817 kfree(pe); in mvpp2_prs_double_vlan_find()
1827 struct mvpp2_prs_entry *pe; in mvpp2_prs_double_vlan_add() local
1830 pe = mvpp2_prs_double_vlan_find(priv, tpid1, tpid2); in mvpp2_prs_double_vlan_add()
1832 if (!pe) { in mvpp2_prs_double_vlan_add()
1839 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_double_vlan_add()
1840 if (!pe) in mvpp2_prs_double_vlan_add()
1859 pe->index = tid_aux; in mvpp2_prs_double_vlan_add()
1860 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_double_vlan_add()
1861 ri_bits = mvpp2_prs_sram_ri_get(pe); in mvpp2_prs_double_vlan_add()
1873 memset(pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_double_vlan_add()
1874 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
1875 pe->index = tid; in mvpp2_prs_double_vlan_add()
1879 mvpp2_prs_match_etype(pe, 0, tpid1); in mvpp2_prs_double_vlan_add()
1880 mvpp2_prs_match_etype(pe, 4, tpid2); in mvpp2_prs_double_vlan_add()
1882 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
1884 mvpp2_prs_sram_shift_set(pe, 2 * MVPP2_VLAN_TAG_LEN, in mvpp2_prs_double_vlan_add()
1886 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_double_vlan_add()
1888 mvpp2_prs_sram_ai_update(pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_double_vlan_add()
1891 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
1895 mvpp2_prs_tcam_port_map_set(pe, port_map); in mvpp2_prs_double_vlan_add()
1896 mvpp2_prs_hw_write(priv, pe); in mvpp2_prs_double_vlan_add()
1899 kfree(pe); in mvpp2_prs_double_vlan_add()
1907 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_proto() local
1920 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip4_proto()
1921 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
1922 pe.index = tid; in mvpp2_prs_ip4_proto()
1925 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
1926 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_proto()
1928 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip4_proto()
1931 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_proto()
1933 mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_MASK, in mvpp2_prs_ip4_proto()
1936 mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip4_proto()
1937 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_proto()
1939 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_proto()
1942 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
1943 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
1951 pe.index = tid; in mvpp2_prs_ip4_proto()
1953 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_ip4_proto()
1954 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_ip4_proto()
1955 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip4_proto()
1957 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, MVPP2_PRS_TCAM_PROTO_MASK_L); in mvpp2_prs_ip4_proto()
1958 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip4_proto()
1961 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
1962 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
1970 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_cast() local
1978 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip4_cast()
1979 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
1980 pe.index = tid; in mvpp2_prs_ip4_cast()
1984 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC, in mvpp2_prs_ip4_cast()
1986 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip4_cast()
1991 mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask); in mvpp2_prs_ip4_cast()
1992 mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask); in mvpp2_prs_ip4_cast()
1993 mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask); in mvpp2_prs_ip4_cast()
1994 mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask); in mvpp2_prs_ip4_cast()
1995 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST, in mvpp2_prs_ip4_cast()
2003 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_cast()
2004 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_cast()
2006 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_cast()
2009 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_cast()
2012 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
2013 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_cast()
2022 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_proto() local
2034 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_proto()
2035 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
2036 pe.index = tid; in mvpp2_prs_ip6_proto()
2039 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_proto()
2040 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_proto()
2041 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip6_proto()
2042 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_proto()
2046 mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip6_proto()
2047 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_proto()
2050 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_proto()
2053 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
2054 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_proto()
2062 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_cast() local
2073 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_cast()
2074 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
2075 pe.index = tid; in mvpp2_prs_ip6_cast()
2078 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
2079 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip6_cast()
2081 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_cast()
2084 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_cast()
2086 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC, in mvpp2_prs_ip6_cast()
2088 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_cast()
2090 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_cast()
2093 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
2094 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_cast()
2129 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow_init() local
2133 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_def_flow_init()
2134 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
2135 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
2138 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_def_flow_init()
2141 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
2142 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow_init()
2145 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
2146 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_def_flow_init()
2153 struct mvpp2_prs_entry pe; in mvpp2_prs_mh_init() local
2155 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mh_init()
2157 pe.index = MVPP2_PE_MH_DEFAULT; in mvpp2_prs_mh_init()
2158 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
2159 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, in mvpp2_prs_mh_init()
2161 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mh_init()
2164 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mh_init()
2167 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
2168 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mh_init()
2176 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_init() local
2178 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_init()
2181 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; in mvpp2_prs_mac_init()
2182 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
2184 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_init()
2186 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_init()
2187 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_init()
2190 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mac_init()
2193 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
2194 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_init()
2206 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_init() local
2239 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_dsa_init()
2240 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_init()
2241 pe.index = MVPP2_PE_DSA_DEFAULT; in mvpp2_prs_dsa_init()
2242 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_init()
2245 mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_dsa_init()
2246 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_dsa_init()
2249 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_dsa_init()
2252 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_dsa_init()
2254 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_init()
2260 struct mvpp2_prs_entry pe; in mvpp2_prs_etype_init() local
2269 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2270 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2271 pe.index = tid; in mvpp2_prs_etype_init()
2273 mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES); in mvpp2_prs_etype_init()
2275 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, in mvpp2_prs_etype_init()
2277 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_etype_init()
2278 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
2282 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2283 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2284 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2285 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
2287 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2295 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2296 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2297 pe.index = tid; in mvpp2_prs_etype_init()
2299 mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP); in mvpp2_prs_etype_init()
2302 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2303 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2304 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
2307 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2312 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2313 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2314 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2315 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
2317 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2325 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2326 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2327 pe.index = tid; in mvpp2_prs_etype_init()
2329 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); in mvpp2_prs_etype_init()
2332 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2333 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2334 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2339 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2344 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2345 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2346 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2347 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2351 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2359 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2360 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2361 pe.index = tid; in mvpp2_prs_etype_init()
2363 mvpp2_prs_match_etype(&pe, 0, ETH_P_IP); in mvpp2_prs_etype_init()
2364 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
2369 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_etype_init()
2370 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
2373 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_etype_init()
2376 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2381 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2382 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2383 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2384 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
2386 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2394 pe.index = tid; in mvpp2_prs_etype_init()
2397 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0; in mvpp2_prs_etype_init()
2398 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0; in mvpp2_prs_etype_init()
2400 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
2405 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_etype_init()
2406 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_etype_init()
2407 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
2411 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2412 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2413 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2414 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
2416 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2424 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2425 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2426 pe.index = tid; in mvpp2_prs_etype_init()
2428 mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6); in mvpp2_prs_etype_init()
2431 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + in mvpp2_prs_etype_init()
2434 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_etype_init()
2435 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
2438 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2442 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2443 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2444 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2445 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
2447 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2450 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2451 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2452 pe.index = MVPP2_PE_ETH_TYPE_UN; in mvpp2_prs_etype_init()
2455 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_etype_init()
2458 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2459 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2460 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
2463 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2468 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2469 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2470 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2471 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
2473 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2487 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_init() local
2521 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_vlan_init()
2522 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
2523 pe.index = MVPP2_PE_VLAN_DBL; in mvpp2_prs_vlan_init()
2525 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_init()
2527 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_init()
2528 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_vlan_init()
2531 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_vlan_init()
2534 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
2537 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
2538 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
2541 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_vlan_init()
2542 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
2543 pe.index = MVPP2_PE_VLAN_NONE; in mvpp2_prs_vlan_init()
2545 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_init()
2546 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_vlan_init()
2550 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
2553 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
2554 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
2562 struct mvpp2_prs_entry pe; in mvpp2_prs_pppoe_init() local
2571 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_pppoe_init()
2572 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2573 pe.index = tid; in mvpp2_prs_pppoe_init()
2575 mvpp2_prs_match_etype(&pe, 0, PPP_IP); in mvpp2_prs_pppoe_init()
2577 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_pppoe_init()
2578 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_pppoe_init()
2581 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_pppoe_init()
2584 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
2589 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2590 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
2598 pe.index = tid; in mvpp2_prs_pppoe_init()
2600 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_pppoe_init()
2606 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_pppoe_init()
2607 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_pppoe_init()
2608 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_pppoe_init()
2612 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2613 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
2621 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_pppoe_init()
2622 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2623 pe.index = tid; in mvpp2_prs_pppoe_init()
2625 mvpp2_prs_match_etype(&pe, 0, PPP_IPV6); in mvpp2_prs_pppoe_init()
2627 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_pppoe_init()
2628 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_pppoe_init()
2631 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_pppoe_init()
2634 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
2639 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2640 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
2648 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_pppoe_init()
2649 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2650 pe.index = tid; in mvpp2_prs_pppoe_init()
2652 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_pppoe_init()
2656 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_pppoe_init()
2657 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_pppoe_init()
2659 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
2664 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2665 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
2673 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_init() local
2706 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip4_init()
2707 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2708 pe.index = MVPP2_PE_IP4_PROTO_UN; in mvpp2_prs_ip4_init()
2711 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2712 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_init()
2714 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip4_init()
2717 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
2719 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip4_init()
2722 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_init()
2724 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
2727 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2728 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
2731 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip4_init()
2732 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2733 pe.index = MVPP2_PE_IP4_ADDR_UN; in mvpp2_prs_ip4_init()
2736 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_init()
2737 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_init()
2738 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip4_init()
2741 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
2744 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
2747 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2748 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
2756 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_init() local
2799 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
2800 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2801 pe.index = tid; in mvpp2_prs_ip6_init()
2804 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
2805 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
2806 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN | in mvpp2_prs_ip6_init()
2811 mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK); in mvpp2_prs_ip6_init()
2812 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
2816 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
2817 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
2820 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
2821 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2822 pe.index = MVPP2_PE_IP6_PROTO_UN; in mvpp2_prs_ip6_init()
2825 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
2826 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
2827 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
2830 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_init()
2834 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
2837 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
2840 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
2841 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
2844 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
2845 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2846 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN; in mvpp2_prs_ip6_init()
2849 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
2850 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
2851 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
2854 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT, in mvpp2_prs_ip6_init()
2857 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
2860 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
2861 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
2864 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
2865 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2866 pe.index = MVPP2_PE_IP6_ADDR_UN; in mvpp2_prs_ip6_init()
2869 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2870 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip6_init()
2872 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
2875 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_init()
2877 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_init()
2879 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
2882 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2883 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
2955 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, in mvpp2_prs_mac_range_equals() argument
2962 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); in mvpp2_prs_mac_range_equals()
2978 struct mvpp2_prs_entry *pe; in mvpp2_prs_mac_da_range_find() local
2981 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_mac_da_range_find()
2982 if (!pe) in mvpp2_prs_mac_da_range_find()
2984 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_range_find()
2996 pe->index = tid; in mvpp2_prs_mac_da_range_find()
2997 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_mac_da_range_find()
2998 entry_pmap = mvpp2_prs_tcam_port_map_get(pe); in mvpp2_prs_mac_da_range_find()
3000 if (mvpp2_prs_mac_range_equals(pe, da, mask) && in mvpp2_prs_mac_da_range_find()
3002 return pe; in mvpp2_prs_mac_da_range_find()
3004 kfree(pe); in mvpp2_prs_mac_da_range_find()
3013 struct mvpp2_prs_entry *pe; in mvpp2_prs_mac_da_accept() local
3019 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, in mvpp2_prs_mac_da_accept()
3023 if (!pe) { in mvpp2_prs_mac_da_accept()
3043 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_mac_da_accept()
3044 if (!pe) in mvpp2_prs_mac_da_accept()
3046 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
3047 pe->index = tid; in mvpp2_prs_mac_da_accept()
3050 mvpp2_prs_tcam_port_map_set(pe, 0); in mvpp2_prs_mac_da_accept()
3054 mvpp2_prs_tcam_port_set(pe, port, add); in mvpp2_prs_mac_da_accept()
3057 pmap = mvpp2_prs_tcam_port_map_get(pe); in mvpp2_prs_mac_da_accept()
3060 kfree(pe); in mvpp2_prs_mac_da_accept()
3063 mvpp2_prs_hw_inv(priv, pe->index); in mvpp2_prs_mac_da_accept()
3064 priv->prs_shadow[pe->index].valid = false; in mvpp2_prs_mac_da_accept()
3065 kfree(pe); in mvpp2_prs_mac_da_accept()
3070 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_da_accept()
3075 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff); in mvpp2_prs_mac_da_accept()
3085 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
3087 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
3091 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN, in mvpp2_prs_mac_da_accept()
3095 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF; in mvpp2_prs_mac_da_accept()
3096 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
3097 mvpp2_prs_hw_write(priv, pe); in mvpp2_prs_mac_da_accept()
3099 kfree(pe); in mvpp2_prs_mac_da_accept()
3129 struct mvpp2_prs_entry pe; in mvpp2_prs_mcast_del_all() local
3142 pe.index = tid; in mvpp2_prs_mcast_del_all()
3143 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mcast_del_all()
3147 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index], in mvpp2_prs_mcast_del_all()
3209 struct mvpp2_prs_entry *pe; in mvpp2_prs_def_flow() local
3212 pe = mvpp2_prs_flow_find(port->priv, port->id); in mvpp2_prs_def_flow()
3215 if (!pe) { in mvpp2_prs_def_flow()
3223 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_def_flow()
3224 if (!pe) in mvpp2_prs_def_flow()
3227 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
3228 pe->index = tid; in mvpp2_prs_def_flow()
3231 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
3232 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow()
3235 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
3238 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); in mvpp2_prs_def_flow()
3239 mvpp2_prs_hw_write(port->priv, pe); in mvpp2_prs_def_flow()
3240 kfree(pe); in mvpp2_prs_def_flow()