Lines Matching refs:MVPP2_RXQ_CONFIG_REG
46 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) macro
3498 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_long_pool_set()
3503 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
3516 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_short_pool_set()
3521 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_short_pool_set()
3967 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_defaults_set()
3970 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
3985 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_enable()
3987 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
3998 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_disable()
4000 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
4108 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_offset_set()
4115 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()