Lines Matching refs:mvreg_write
484 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) in mvreg_write() function
583 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), in mvneta_rxq_non_occup_desc_add()
589 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), in mvneta_rxq_non_occup_desc_add()
615 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); in mvneta_rxq_desc_num_update()
635 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); in mvneta_rxq_desc_num_update()
659 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); in mvneta_max_rx_size_set()
675 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); in mvneta_rxq_offset_set()
692 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); in mvneta_txq_pend_desc_add()
728 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); in mvneta_rxq_buf_size_set()
739 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); in mvneta_rxq_bm_disable()
756 mvreg_write(pp, MVNETA_TXQ_CMD, q_map); in mvneta_port_up()
766 mvreg_write(pp, MVNETA_RXQ_CMD, q_map); in mvneta_port_up()
780 mvreg_write(pp, MVNETA_RXQ_CMD, in mvneta_port_down()
803 mvreg_write(pp, MVNETA_TXQ_CMD, in mvneta_port_down()
848 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); in mvneta_port_enable()
859 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); in mvneta_port_disable()
880 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); in mvneta_set_ucast_table()
897 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); in mvneta_set_special_mcast_table()
917 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); in mvneta_set_other_mcast_table()
936 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); in mvneta_defaults_set()
937 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); in mvneta_defaults_set()
938 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); in mvneta_defaults_set()
941 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); in mvneta_defaults_set()
942 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); in mvneta_defaults_set()
943 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); in mvneta_defaults_set()
944 mvreg_write(pp, MVNETA_INTR_ENABLE, 0); in mvneta_defaults_set()
947 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); in mvneta_defaults_set()
953 mvreg_write(pp, MVNETA_CPU_MAP(cpu), in mvneta_defaults_set()
958 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); in mvneta_defaults_set()
959 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); in mvneta_defaults_set()
962 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); in mvneta_defaults_set()
964 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); in mvneta_defaults_set()
965 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); in mvneta_defaults_set()
968 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); in mvneta_defaults_set()
969 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); in mvneta_defaults_set()
973 mvreg_write(pp, MVNETA_ACC_MODE, val); in mvneta_defaults_set()
977 mvreg_write(pp, MVNETA_PORT_CONFIG, val); in mvneta_defaults_set()
980 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); in mvneta_defaults_set()
981 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); in mvneta_defaults_set()
996 mvreg_write(pp, MVNETA_SDMA_CONFIG, val); in mvneta_defaults_set()
1003 mvreg_write(pp, MVNETA_UNIT_CONTROL, val); in mvneta_defaults_set()
1013 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); in mvneta_defaults_set()
1016 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); in mvneta_defaults_set()
1022 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); in mvneta_defaults_set()
1030 mvreg_write(pp, MVNETA_INTR_ENABLE, in mvneta_defaults_set()
1050 mvreg_write(pp, MVNETA_TX_MTU, val); in mvneta_txq_max_tx_size_set()
1060 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); in mvneta_txq_max_tx_size_set()
1070 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); in mvneta_txq_max_tx_size_set()
1102 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); in mvneta_set_ucast_addr()
1117 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); in mvneta_mac_addr_set()
1118 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); in mvneta_mac_addr_set()
1131 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), in mvneta_rx_pkts_coal_set()
1148 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); in mvneta_rx_time_coal_set()
1163 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); in mvneta_tx_done_pkts_coal_set()
1186 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); in mvneta_txq_sent_desc_dec()
1191 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); in mvneta_txq_sent_desc_dec()
1919 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, in mvneta_set_special_mcast_addr()
1952 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); in mvneta_set_other_mcast_addr()
2012 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); in mvneta_rx_unicast_promisc_set()
2013 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); in mvneta_rx_unicast_promisc_set()
2020 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); in mvneta_rx_unicast_promisc_set()
2021 mvreg_write(pp, MVNETA_TYPE_PRIO, val); in mvneta_rx_unicast_promisc_set()
2067 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); in mvneta_isr()
2120 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); in mvneta_poll()
2171 mvreg_write(pp, MVNETA_INTR_NEW_MASK, in mvneta_poll()
2214 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); in mvneta_tx_reset()
2215 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); in mvneta_tx_reset()
2220 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); in mvneta_rx_reset()
2221 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); in mvneta_rx_reset()
2246 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); in mvneta_rxq_init()
2247 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); in mvneta_rxq_init()
2310 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); in mvneta_txq_init()
2311 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); in mvneta_txq_init()
2314 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); in mvneta_txq_init()
2315 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); in mvneta_txq_init()
2362 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); in mvneta_txq_deinit()
2363 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); in mvneta_txq_deinit()
2366 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); in mvneta_txq_deinit()
2367 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); in mvneta_txq_deinit()
2437 mvreg_write(pp, MVNETA_INTR_NEW_MASK, in mvneta_start_dev()
2441 mvreg_write(pp, MVNETA_INTR_MISC_MASK, in mvneta_start_dev()
2465 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); in mvneta_stop_dev()
2466 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); in mvneta_stop_dev()
2469 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); in mvneta_stop_dev()
2470 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); in mvneta_stop_dev()
2471 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); in mvneta_stop_dev()
2623 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); in mvneta_adjust_link()
2647 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, in mvneta_adjust_link()
2657 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, in mvneta_adjust_link()
2951 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); in mvneta_conf_mbus_windows()
2952 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); in mvneta_conf_mbus_windows()
2955 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); in mvneta_conf_mbus_windows()
2963 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | in mvneta_conf_mbus_windows()
2966 mvreg_write(pp, MVNETA_WIN_SIZE(i), in mvneta_conf_mbus_windows()
2973 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); in mvneta_conf_mbus_windows()
2982 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); in mvneta_port_power_up()
2991 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); in mvneta_port_power_up()
2995 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); in mvneta_port_power_up()
3011 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); in mvneta_port_power_up()