Lines Matching refs:adap
112 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, in t4_read_indirect() argument
117 t4_write_reg(adap, addr_reg, start_idx); in t4_read_indirect()
118 *vals++ = t4_read_reg(adap, data_reg); in t4_read_indirect()
135 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, in t4_write_indirect() argument
140 t4_write_reg(adap, addr_reg, start_idx++); in t4_write_indirect()
141 t4_write_reg(adap, data_reg, *vals++); in t4_write_indirect()
151 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val) in t4_hw_pci_read_cfg4() argument
153 u32 req = ENABLE_F | FUNCTION_V(adap->fn) | REGISTER_V(reg); in t4_hw_pci_read_cfg4()
155 if (is_t4(adap->params.chip)) in t4_hw_pci_read_cfg4()
158 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req); in t4_hw_pci_read_cfg4()
159 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A); in t4_hw_pci_read_cfg4()
166 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); in t4_hw_pci_read_cfg4()
177 static void t4_report_fw_error(struct adapter *adap) in t4_report_fw_error() argument
191 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in t4_report_fw_error()
193 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n", in t4_report_fw_error()
200 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, in get_mbox_rpl() argument
204 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); in get_mbox_rpl()
210 static void fw_asrt(struct adapter *adap, u32 mbox_addr) in fw_asrt() argument
214 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr); in fw_asrt()
215 dev_alert(adap->pdev_dev, in fw_asrt()
221 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg) in dump_mbox() argument
223 dev_err(adap->pdev_dev, in dump_mbox()
225 (unsigned long long)t4_read_reg64(adap, data_reg), in dump_mbox()
226 (unsigned long long)t4_read_reg64(adap, data_reg + 8), in dump_mbox()
227 (unsigned long long)t4_read_reg64(adap, data_reg + 16), in dump_mbox()
228 (unsigned long long)t4_read_reg64(adap, data_reg + 24), in dump_mbox()
229 (unsigned long long)t4_read_reg64(adap, data_reg + 32), in dump_mbox()
230 (unsigned long long)t4_read_reg64(adap, data_reg + 40), in dump_mbox()
231 (unsigned long long)t4_read_reg64(adap, data_reg + 48), in dump_mbox()
232 (unsigned long long)t4_read_reg64(adap, data_reg + 56)); in dump_mbox()
257 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, in t4_wr_mbox_meat() argument
278 if (adap->pdev->error_state != pci_channel_io_normal) in t4_wr_mbox_meat()
281 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat()
283 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat()
289 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++)); in t4_wr_mbox_meat()
291 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW)); in t4_wr_mbox_meat()
292 t4_read_reg(adap, ctl_reg); /* flush write */ in t4_wr_mbox_meat()
306 v = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat()
309 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat()
313 res = t4_read_reg64(adap, data_reg); in t4_wr_mbox_meat()
315 fw_asrt(adap, data_reg); in t4_wr_mbox_meat()
318 get_mbox_rpl(adap, rpl, size / 8, data_reg); in t4_wr_mbox_meat()
322 dump_mbox(adap, mbox, data_reg); in t4_wr_mbox_meat()
323 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat()
328 dump_mbox(adap, mbox, data_reg); in t4_wr_mbox_meat()
329 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n", in t4_wr_mbox_meat()
331 t4_report_fw_error(adap); in t4_wr_mbox_meat()
347 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) in t4_mc_read() argument
353 if (is_t4(adap->params.chip)) { in t4_mc_read()
367 if (t4_read_reg(adap, mc_bist_cmd) & START_BIST_F) in t4_mc_read()
369 t4_write_reg(adap, mc_bist_cmd_addr, addr & ~0x3fU); in t4_mc_read()
370 t4_write_reg(adap, mc_bist_cmd_len, 64); in t4_mc_read()
371 t4_write_reg(adap, mc_bist_data_pattern, 0xc); in t4_mc_read()
372 t4_write_reg(adap, mc_bist_cmd, BIST_OPCODE_V(1) | START_BIST_F | in t4_mc_read()
374 i = t4_wait_op_done(adap, mc_bist_cmd, START_BIST_F, 0, 10, 1); in t4_mc_read()
381 *data++ = htonl(t4_read_reg(adap, MC_DATA(i))); in t4_mc_read()
383 *ecc = t4_read_reg64(adap, MC_DATA(16)); in t4_mc_read()
400 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) in t4_edc_read() argument
406 if (is_t4(adap->params.chip)) { in t4_edc_read()
424 if (t4_read_reg(adap, edc_bist_cmd) & START_BIST_F) in t4_edc_read()
426 t4_write_reg(adap, edc_bist_cmd_addr, addr & ~0x3fU); in t4_edc_read()
427 t4_write_reg(adap, edc_bist_cmd_len, 64); in t4_edc_read()
428 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); in t4_edc_read()
429 t4_write_reg(adap, edc_bist_cmd, in t4_edc_read()
431 i = t4_wait_op_done(adap, edc_bist_cmd, START_BIST_F, 0, 10, 1); in t4_edc_read()
438 *data++ = htonl(t4_read_reg(adap, EDC_DATA(i))); in t4_edc_read()
440 *ecc = t4_read_reg64(adap, EDC_DATA(16)); in t4_edc_read()
462 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, in t4_memory_rw() argument
490 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A)); in t4_memory_rw()
494 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap, in t4_memory_rw()
510 mem_reg = t4_read_reg(adap, in t4_memory_rw()
515 if (is_t4(adap->params.chip)) in t4_memory_rw()
516 mem_base -= adap->t4_bar0; in t4_memory_rw()
517 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->fn); in t4_memory_rw()
529 t4_write_reg(adap, in t4_memory_rw()
532 t4_read_reg(adap, in t4_memory_rw()
571 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap, in t4_memory_rw()
574 t4_write_reg(adap, mem_base + offset, in t4_memory_rw()
588 t4_write_reg(adap, in t4_memory_rw()
591 t4_read_reg(adap, in t4_memory_rw()
612 (__force __le32)t4_read_reg(adap, in t4_memory_rw()
620 t4_write_reg(adap, mem_base + offset, in t4_memory_rw()
661 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size) in t4_get_regs() argument
1315 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_get_regs()
1332 dev_err(adap->pdev_dev, in t4_get_regs()
1350 *bufp++ = t4_read_reg(adap, reg); in t4_get_regs()
1723 int t4_get_exprom_version(struct adapter *adap, u32 *vers) in t4_get_exprom_version() argument
1733 ret = t4_read_flash(adap, FLASH_EXP_ROM_START, in t4_get_exprom_version()
1773 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable, in should_install_fs_fw() argument
1791 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, " in should_install_fs_fw()
1801 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, in t4_prep_fw() argument
1813 ret = -t4_read_flash(adap, FLASH_FW_START, in t4_prep_fw()
1819 dev_err(adap->pdev_dev, in t4_prep_fw()
1839 should_install_fs_fw(adap, card_fw_usable, in t4_prep_fw()
1842 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data, in t4_prep_fw()
1845 dev_err(adap->pdev_dev, in t4_prep_fw()
1863 dev_err(adap->pdev_dev, "Cannot find a usable firmware: " in t4_prep_fw()
1879 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver); in t4_prep_fw()
1880 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); in t4_prep_fw()
1937 static bool t4_fw_matches_chip(const struct adapter *adap, in t4_fw_matches_chip() argument
1943 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) || in t4_fw_matches_chip()
1944 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5)) in t4_fw_matches_chip()
1947 dev_err(adap->pdev_dev, in t4_fw_matches_chip()
1949 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip)); in t4_fw_matches_chip()
1961 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) in t4_load_fw() argument
1969 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_fw()
1970 unsigned int fw_img_start = adap->params.sf_fw_start; in t4_load_fw()
1974 dev_err(adap->pdev_dev, "FW image has no data\n"); in t4_load_fw()
1978 dev_err(adap->pdev_dev, in t4_load_fw()
1983 dev_err(adap->pdev_dev, in t4_load_fw()
1988 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n", in t4_load_fw()
1992 if (!t4_fw_matches_chip(adap, hdr)) in t4_load_fw()
1999 dev_err(adap->pdev_dev, in t4_load_fw()
2005 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); in t4_load_fw()
2016 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page); in t4_load_fw()
2024 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data); in t4_load_fw()
2029 ret = t4_write_flash(adap, in t4_load_fw()
2034 dev_err(adap->pdev_dev, "firmware download failed, error %d\n", in t4_load_fw()
2037 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_load_fw()
2046 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) in t4_fwcache() argument
2054 FW_PARAMS_CMD_PFN_V(adap->fn) | in t4_fwcache()
2062 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); in t4_fwcache()
2065 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) in t4_ulprx_read_la() argument
2072 t4_write_reg(adap, ULP_RX_LA_CTL_A, i); in t4_ulprx_read_la()
2073 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A); in t4_ulprx_read_la()
2074 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j); in t4_ulprx_read_la()
2076 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A); in t4_ulprx_read_la()
2097 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, in t4_link_start() argument
2124 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_link_start()
2135 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) in t4_restart_aneg() argument
2145 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_restart_aneg()
2148 typedef void (*int_handler_t)(struct adapter *adap);
2548 static void le_intr_handler(struct adapter *adap) in le_intr_handler() argument
2559 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A, le_intr_info)) in le_intr_handler()
2560 t4_fatal_err(adap); in le_intr_handler()
2686 static void ma_intr_handler(struct adapter *adap) in ma_intr_handler() argument
2688 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A); in ma_intr_handler()
2691 dev_alert(adap->pdev_dev, in ma_intr_handler()
2693 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A)); in ma_intr_handler()
2694 if (is_t5(adap->params.chip)) in ma_intr_handler()
2695 dev_alert(adap->pdev_dev, in ma_intr_handler()
2697 t4_read_reg(adap, in ma_intr_handler()
2701 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A); in ma_intr_handler()
2702 dev_alert(adap->pdev_dev, "MA address wrap-around error by " in ma_intr_handler()
2707 t4_write_reg(adap, MA_INT_CAUSE_A, status); in ma_intr_handler()
2708 t4_fatal_err(adap); in ma_intr_handler()
2714 static void smb_intr_handler(struct adapter *adap) in smb_intr_handler() argument
2723 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info)) in smb_intr_handler()
2724 t4_fatal_err(adap); in smb_intr_handler()
2730 static void ncsi_intr_handler(struct adapter *adap) in ncsi_intr_handler() argument
2740 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info)) in ncsi_intr_handler()
2741 t4_fatal_err(adap); in ncsi_intr_handler()
2747 static void xgmac_intr_handler(struct adapter *adap, int port) in xgmac_intr_handler() argument
2751 if (is_t4(adap->params.chip)) in xgmac_intr_handler()
2756 v = t4_read_reg(adap, int_cause_reg); in xgmac_intr_handler()
2763 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n", in xgmac_intr_handler()
2766 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n", in xgmac_intr_handler()
2768 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v); in xgmac_intr_handler()
2769 t4_fatal_err(adap); in xgmac_intr_handler()
2775 static void pl_intr_handler(struct adapter *adap) in pl_intr_handler() argument
2783 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info)) in pl_intr_handler()
2784 t4_fatal_err(adap); in pl_intr_handler()
3018 static int rd_rss_row(struct adapter *adap, int row, u32 *val) in rd_rss_row() argument
3020 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row); in rd_rss_row()
3021 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1, in rd_rss_row()
3054 void t4_read_rss_key(struct adapter *adap, u32 *key) in t4_read_rss_key() argument
3056 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, in t4_read_rss_key()
3070 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx) in t4_write_rss_key() argument
3072 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, in t4_write_rss_key()
3075 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, in t4_write_rss_key()
3167 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, in t4_tp_get_tcp_stats() argument
3177 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, in t4_tp_get_tcp_stats()
3185 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, in t4_tp_get_tcp_stats()
3205 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) in t4_read_mtu_tbl() argument
3211 t4_write_reg(adap, TP_MTU_TABLE_A, in t4_read_mtu_tbl()
3213 v = t4_read_reg(adap, TP_MTU_TABLE_A); in t4_read_mtu_tbl()
3228 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) in t4_read_cong_tbl() argument
3234 t4_write_reg(adap, TP_CCTRL_TABLE_A, in t4_read_cong_tbl()
3236 incr[mtu][w] = (u16)t4_read_reg(adap, in t4_read_cong_tbl()
3250 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, in t4_tp_wr_bits_indirect() argument
3253 t4_write_reg(adap, TP_PIO_ADDR_A, addr); in t4_tp_wr_bits_indirect()
3254 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask; in t4_tp_wr_bits_indirect()
3255 t4_write_reg(adap, TP_PIO_DATA_A, val); in t4_tp_wr_bits_indirect()
3317 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, in t4_load_mtus() argument
3334 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) | in t4_load_mtus()
3343 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) | in t4_load_mtus()
3357 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) in t4_pmtx_get_stats() argument
3363 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1); in t4_pmtx_get_stats()
3364 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A); in t4_pmtx_get_stats()
3365 if (is_t4(adap->params.chip)) { in t4_pmtx_get_stats()
3366 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A); in t4_pmtx_get_stats()
3368 t4_read_indirect(adap, PM_TX_DBG_CTRL_A, in t4_pmtx_get_stats()
3384 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) in t4_pmrx_get_stats() argument
3390 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1); in t4_pmrx_get_stats()
3391 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A); in t4_pmrx_get_stats()
3392 if (is_t4(adap->params.chip)) { in t4_pmrx_get_stats()
3393 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A); in t4_pmrx_get_stats()
3395 t4_read_indirect(adap, PM_RX_DBG_CTRL_A, in t4_pmrx_get_stats()
3412 static unsigned int get_mps_bg_map(struct adapter *adap, int idx) in get_mps_bg_map() argument
3414 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A)); in get_mps_bg_map()
3461 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) in t4_get_port_stats() argument
3463 u32 bgmap = get_mps_bg_map(adap, idx); in t4_get_port_stats()
3466 t4_read_reg64(adap, \ in t4_get_port_stats()
3467 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ in t4_get_port_stats()
3469 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) in t4_get_port_stats()
3544 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, in t4_wol_magic_enable() argument
3549 if (is_t4(adap->params.chip)) { in t4_wol_magic_enable()
3560 t4_write_reg(adap, mag_id_reg_l, in t4_wol_magic_enable()
3563 t4_write_reg(adap, mag_id_reg_h, in t4_wol_magic_enable()
3566 t4_set_reg_field(adap, port_cfg_reg, MAGICEN_F, in t4_wol_magic_enable()
3585 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, in t4_wol_pat_enable() argument
3591 if (is_t4(adap->params.chip)) in t4_wol_pat_enable()
3597 t4_set_reg_field(adap, port_cfg_reg, PATEN_F, 0); in t4_wol_pat_enable()
3604 (is_t4(adap->params.chip) ? \ in t4_wol_pat_enable()
3608 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); in t4_wol_pat_enable()
3609 t4_write_reg(adap, EPIO_REG(DATA2), mask1); in t4_wol_pat_enable()
3610 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); in t4_wol_pat_enable()
3617 t4_write_reg(adap, EPIO_REG(DATA0), mask0); in t4_wol_pat_enable()
3618 t4_write_reg(adap, EPIO_REG(OP), ADDRESS_V(i) | EPIOWR_F); in t4_wol_pat_enable()
3619 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ in t4_wol_pat_enable()
3620 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY_F) in t4_wol_pat_enable()
3624 t4_write_reg(adap, EPIO_REG(DATA0), crc); in t4_wol_pat_enable()
3625 t4_write_reg(adap, EPIO_REG(OP), ADDRESS_V(i + 32) | EPIOWR_F); in t4_wol_pat_enable()
3626 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ in t4_wol_pat_enable()
3627 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY_F) in t4_wol_pat_enable()
3632 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2_A), 0, PATEN_F); in t4_wol_pat_enable()
3662 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, in t4_fwaddrspace_write() argument
3675 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fwaddrspace_write()
3689 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, in t4_mdio_rd() argument
3703 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_mdio_rd()
3720 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, in t4_mdio_wr() argument
3734 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_mdio_wr()
3854 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, in t4_fw_hello() argument
3882 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_fw_hello()
3886 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F) in t4_fw_hello()
3887 t4_report_fw_error(adap); in t4_fw_hello()
3936 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in t4_fw_hello()
3980 int t4_fw_bye(struct adapter *adap, unsigned int mbox) in t4_fw_bye() argument
3986 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fw_bye()
3997 int t4_early_init(struct adapter *adap, unsigned int mbox) in t4_early_init() argument
4003 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_early_init()
4014 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) in t4_fw_reset() argument
4021 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fw_reset()
4040 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) in t4_fw_halt() argument
4055 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fw_halt()
4072 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F); in t4_fw_halt()
4073 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, in t4_fw_halt()
4105 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) in t4_fw_restart() argument
4113 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0); in t4_fw_restart()
4123 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); in t4_fw_restart()
4125 if (t4_fw_reset(adap, mbox, in t4_fw_restart()
4130 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F); in t4_fw_restart()
4135 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); in t4_fw_restart()
4137 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F)) in t4_fw_restart()
4168 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, in t4_fw_upgrade() argument
4174 if (!t4_fw_matches_chip(adap, fw_hdr)) in t4_fw_upgrade()
4177 ret = t4_fw_halt(adap, mbox, force); in t4_fw_upgrade()
4181 ret = t4_load_fw(adap, fw_data, size); in t4_fw_upgrade()
4194 return t4_fw_restart(adap, mbox, reset); in t4_fw_upgrade()
4207 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, in t4_fixup_host_params() argument
4216 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A, in t4_fixup_host_params()
4226 if (is_t4(adap->params.chip)) { in t4_fixup_host_params()
4227 t4_set_reg_field(adap, SGE_CONTROL_A, in t4_fixup_host_params()
4262 t4_set_reg_field(adap, SGE_CONTROL_A, in t4_fixup_host_params()
4267 t4_set_reg_field(adap, SGE_CONTROL2_A, in t4_fixup_host_params()
4293 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size); in t4_fixup_host_params()
4294 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A, in t4_fixup_host_params()
4295 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1) in t4_fixup_host_params()
4297 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A, in t4_fixup_host_params()
4298 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1) in t4_fixup_host_params()
4301 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12)); in t4_fixup_host_params()
4314 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) in t4_fw_initialize() argument
4320 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fw_initialize()
4336 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_query_params() argument
4355 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_query_params()
4376 int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox, in t4_set_params_nosleep() argument
4399 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); in t4_set_params_nosleep()
4415 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_set_params() argument
4435 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_set_params()
4459 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_cfg_pfvf() argument
4482 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_cfg_pfvf()
4502 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, in t4_alloc_vi() argument
4517 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_alloc_vi()
4553 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_set_rxmode() argument
4580 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); in t4_set_rxmode()
4605 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, in t4_alloc_mac_filt() argument
4612 unsigned int max_naddr = is_t4(adap->params.chip) ? in t4_alloc_mac_filt()
4632 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); in t4_alloc_mac_filt()
4668 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_change_mac() argument
4674 unsigned int max_mac_addr = is_t4(adap->params.chip) ? in t4_change_mac()
4691 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_change_mac()
4711 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_set_addr_hash() argument
4723 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); in t4_set_addr_hash()
4738 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, in t4_enable_vi_params() argument
4750 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); in t4_enable_vi_params()
4763 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_enable_vi() argument
4766 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); in t4_enable_vi()
4778 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_identify_port() argument
4788 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_identify_port()
4804 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_iq_free() argument
4819 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_iq_free()
4832 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_eth_eq_free() argument
4843 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_eth_eq_free()
4856 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_ctrl_eq_free() argument
4867 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_ctrl_eq_free()
4880 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_ofld_eq_free() argument
4891 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_ofld_eq_free()
4901 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) in t4_handle_fw_rpl() argument
4909 int port = adap->chan_map[chan]; in t4_handle_fw_rpl()
4910 struct port_info *pi = adap2pinfo(adap, port); in t4_handle_fw_rpl()
4935 t4_os_link_changed(adap, port, link_ok); in t4_handle_fw_rpl()
4939 t4_os_portmod_changed(adap, port); in t4_handle_fw_rpl()
5000 static int get_flash_params(struct adapter *adap) in get_flash_params() argument
5012 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID); in get_flash_params()
5014 ret = sf1_read(adap, 3, 0, 1, &info); in get_flash_params()
5015 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */ in get_flash_params()
5021 adap->params.sf_size = supported_flash[ret].size_mb; in get_flash_params()
5022 adap->params.sf_nsec = in get_flash_params()
5023 adap->params.sf_size / SF_SEC_SIZE; in get_flash_params()
5031 adap->params.sf_nsec = 1 << (info - 16); in get_flash_params()
5033 adap->params.sf_nsec = 64; in get_flash_params()
5036 adap->params.sf_size = 1 << info; in get_flash_params()
5037 adap->params.sf_fw_start = in get_flash_params()
5038 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M; in get_flash_params()
5040 if (adap->params.sf_size < FLASH_MIN_SIZE) in get_flash_params()
5041 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n", in get_flash_params()
5042 adap->params.sf_size, FLASH_MIN_SIZE); in get_flash_params()
5196 int t4_init_devlog_params(struct adapter *adap) in t4_init_devlog_params() argument
5198 struct devlog_params *dparams = &adap->params.devlog; in t4_init_devlog_params()
5209 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG)); in t4_init_devlog_params()
5229 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), in t4_init_devlog_params()
5279 int t4_init_tp_params(struct adapter *adap) in t4_init_tp_params() argument
5284 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A); in t4_init_tp_params()
5285 adap->params.tp.tre = TIMERRESOLUTION_G(v); in t4_init_tp_params()
5286 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v); in t4_init_tp_params()
5290 adap->params.tp.tx_modq[chan] = chan; in t4_init_tp_params()
5295 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, in t4_init_tp_params()
5296 &adap->params.tp.vlan_pri_map, 1, in t4_init_tp_params()
5298 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, in t4_init_tp_params()
5299 &adap->params.tp.ingress_config, 1, in t4_init_tp_params()
5306 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F); in t4_init_tp_params()
5307 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F); in t4_init_tp_params()
5308 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F); in t4_init_tp_params()
5309 adap->params.tp.protocol_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
5315 if ((adap->params.tp.ingress_config & VNIC_F) == 0) in t4_init_tp_params()
5316 adap->params.tp.vnic_shift = -1; in t4_init_tp_params()
5330 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) in t4_filter_field_shift() argument
5332 unsigned int filter_mode = adap->params.tp.vlan_pri_map; in t4_filter_field_shift()
5376 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf) in t4_port_init() argument
5386 for_each_port(adap, i) { in t4_port_init()
5388 struct port_info *p = adap2pinfo(adap, i); in t4_port_init()
5390 while ((adap->params.portvec & (1 << j)) == 0) in t4_port_init()
5399 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_port_init()
5403 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); in t4_port_init()
5411 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN); in t4_port_init()
5412 adap->port[i]->dev_port = j; in t4_port_init()
5424 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc); in t4_port_init()
5445 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) in t4_read_cimq_cfg() argument
5448 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cimq_cfg()
5452 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F | in t4_read_cimq_cfg()
5454 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); in t4_read_cimq_cfg()
5461 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | in t4_read_cimq_cfg()
5463 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); in t4_read_cimq_cfg()
5481 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) in t4_read_cim_ibq() argument
5500 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) | in t4_read_cim_ibq()
5502 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0, in t4_read_cim_ibq()
5506 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A); in t4_read_cim_ibq()
5508 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0); in t4_read_cim_ibq()
5523 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) in t4_read_cim_obq() argument
5527 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cim_obq()
5533 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | in t4_read_cim_obq()
5535 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); in t4_read_cim_obq()
5543 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) | in t4_read_cim_obq()
5545 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0, in t4_read_cim_obq()
5549 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A); in t4_read_cim_obq()
5551 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0); in t4_read_cim_obq()
5564 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, in t4_cim_read() argument
5569 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) in t4_cim_read()
5573 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr); in t4_cim_read()
5574 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, in t4_cim_read()
5577 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A); in t4_cim_read()
5591 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, in t4_cim_write() argument
5596 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) in t4_cim_write()
5600 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++); in t4_cim_write()
5601 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F); in t4_cim_write()
5602 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, in t4_cim_write()
5608 static int t4_cim_write1(struct adapter *adap, unsigned int addr, in t4_cim_write1() argument
5611 return t4_cim_write(adap, addr, 1, &val); in t4_cim_write1()
5624 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) in t4_cim_read_la() argument
5629 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg); in t4_cim_read_la()
5634 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0); in t4_cim_read_la()
5639 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); in t4_cim_read_la()
5647 for (i = 0; i < adap->params.cim_la_size; i++) { in t4_cim_read_la()
5648 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, in t4_cim_read_la()
5652 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); in t4_cim_read_la()
5659 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]); in t4_cim_read_la()
5666 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, in t4_cim_read_la()
5684 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) in t4_tp_read_la() argument
5689 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff; in t4_tp_read_la()
5691 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, in t4_tp_read_la()
5692 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F)); in t4_tp_read_la()
5694 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A); in t4_tp_read_la()
5704 val |= adap->params.tp.la_mask; in t4_tp_read_la()
5707 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val); in t4_tp_read_la()
5708 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A); in t4_tp_read_la()
5717 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, in t4_tp_read_la()
5718 cfg | adap->params.tp.la_mask); in t4_tp_read_la()