571 		u32 *data = bnx2x_sp(bp, wb_data[0]);  in bnx2x_write_dmae()
606 		u32 *data = bnx2x_sp(bp, wb_data[0]);  in bnx2x_read_dmae()
625 	dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));  in bnx2x_read_dmae()
626 	dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));  in bnx2x_read_dmae()
6658 		val = *bnx2x_sp(bp, wb_data[0]);  in bnx2x_int_mem_test()
6714 		val = *bnx2x_sp(bp, wb_data[0]);  in bnx2x_int_mem_test()
7401 		val = *bnx2x_sp(bp, wb_data[0]);  in bnx2x_init_hw_common()
8176 			bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),  in bnx2x_init_hw_func()
10193 			u32 wb_data[2];  in bnx2x_prev_unload_close_mac()  local
10206 			wb_data[0] = REG_RD(bp, base_addr + offset);  in bnx2x_prev_unload_close_mac()
10207 			wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);  in bnx2x_prev_unload_close_mac()
10209 			vals->bmac_val[0] = wb_data[0];  in bnx2x_prev_unload_close_mac()
10210 			vals->bmac_val[1] = wb_data[1];  in bnx2x_prev_unload_close_mac()
10211 			wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;  in bnx2x_prev_unload_close_mac()
10212 			REG_WR(bp, vals->bmac_addr, wb_data[0]);  in bnx2x_prev_unload_close_mac()
10213 			REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);  in bnx2x_prev_unload_close_mac()
14623 	u32 wb_data[2];  in bnx2x_cyclecounter_read()  local
14627 		    NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);  in bnx2x_cyclecounter_read()
14628 	phc_cycles = wb_data[1];  in bnx2x_cyclecounter_read()
14629 	phc_cycles = (phc_cycles << 32) + wb_data[0];  in bnx2x_cyclecounter_read()
14816 	u32 wb_data[2];  in bnx2x_configure_ptp()  local
14837 	wb_data[0] = 0;  in bnx2x_configure_ptp()
14838 	wb_data[1] = 0;  in bnx2x_configure_ptp()
14839 	REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);  in bnx2x_configure_ptp()