Lines Matching refs:REG_WR
299 REG_WR(bp, addr, U64_LO(mapping)); in __storm_memset_dma_mapping()
300 REG_WR(bp, addr + 4, U64_HI(mapping)); in __storm_memset_dma_mapping()
459 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); in bnx2x_post_dmae()
461 REG_WR(bp, dmae_reg_go_c[idx], 1); in bnx2x_post_dmae()
848 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); in bnx2x_hc_int_disable()
866 REG_WR(bp, addr, val); in bnx2x_hc_int_disable()
884 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_disable()
1397 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); in bnx2x_send_final_clnup()
1407 REG_WR(bp, comp_addr, 0); in bnx2x_send_final_clnup()
1504 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in bnx2x_pf_flr_clnup()
1536 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_pf_flr_clnup()
1572 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1579 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); in bnx2x_hc_int_enable()
1585 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1602 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1603 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1641 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
1650 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
1666 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); in bnx2x_igu_int_enable()
1667 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); in bnx2x_igu_int_enable()
1739 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); in bnx2x_trylock_hw_lock()
2014 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); in bnx2x_acquire_hw_lock()
2059 REG_WR(bp, hw_lock_control_reg, resource_bit); in bnx2x_release_hw_lock()
2141 REG_WR(bp, MISC_REG_GPIO, gpio_reg); in bnx2x_set_gpio()
2187 REG_WR(bp, MISC_REG_GPIO, gpio_reg); in bnx2x_set_mult_gpio()
2236 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); in bnx2x_set_gpio_int()
2281 REG_WR(bp, MISC_REG_SPIO, spio_reg); in bnx2x_set_spio()
2333 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_dropless_fc()
2831 REG_WR(bp, addr_to_write + i*sizeof(u32), in bnx2x_handle_afex_cmd()
2934 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, in bnx2x_handle_update_svid_cmd()
2982 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_pmf_update()
2983 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_pmf_update()
2985 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); in bnx2x_pmf_update()
2986 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); in bnx2x_pmf_update()
3070 REG_WR(bp, XSEM_REG_FAST_MEMORY + in bnx2x_func_init()
3289 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + in bnx2x_pf_init()
3294 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + in bnx2x_pf_init()
3347 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_e1h_disable()
3355 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); in bnx2x_e1h_enable()
3919 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); in bnx2x_acquire_alr()
3937 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); in bnx2x_release_alr()
3990 REG_WR(bp, aeu_addr, aeu_mask); in bnx2x_attn_int_asserted()
4009 REG_WR(bp, nig_int_mask_addr, 0); in bnx2x_attn_int_asserted()
4031 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); in bnx2x_attn_int_asserted()
4035 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); in bnx2x_attn_int_asserted()
4039 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); in bnx2x_attn_int_asserted()
4044 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); in bnx2x_attn_int_asserted()
4048 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); in bnx2x_attn_int_asserted()
4052 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); in bnx2x_attn_int_asserted()
4066 REG_WR(bp, reg_addr, asserted); in bnx2x_attn_int_asserted()
4085 REG_WR(bp, nig_int_mask_addr, nig_mask); in bnx2x_attn_int_asserted()
4128 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
4147 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
4178 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted1()
4222 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted2()
4239 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_attn_int_deasserted3()
4299 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); in bnx2x_attn_int_deasserted3()
4300 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); in bnx2x_attn_int_deasserted3()
4301 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); in bnx2x_attn_int_deasserted3()
4302 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); in bnx2x_attn_int_deasserted3()
4308 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); in bnx2x_attn_int_deasserted3()
4327 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); in bnx2x_attn_int_deasserted3()
4365 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); in bnx2x_set_reset_global()
4379 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); in bnx2x_clear_reset_global()
4411 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_reset_done()
4431 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_reset_in_progress()
4479 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_pf_load()
4516 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_clear_pf_load()
4874 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, in bnx2x_check_blocks_with_parity3()
5133 REG_WR(bp, reg_addr, val); in bnx2x_attn_int_deasserted()
5149 REG_WR(bp, reg_addr, aeu_mask); in bnx2x_attn_int_deasserted()
5779 REG_WR(bp, addr + i, fill); in bnx2x_fill()
5793 REG_WR(bp, BAR_CSTRORM_INTMEM + in bnx2x_wr_fp_sb_data()
5838 REG_WR(bp, BAR_CSTRORM_INTMEM + in bnx2x_wr_sp_sb_data()
6033 REG_WR(bp, reg_offset, U64_LO(section)); in bnx2x_init_def_sb()
6034 REG_WR(bp, reg_offset + 4, U64_HI(section)); in bnx2x_init_def_sb()
6036 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); in bnx2x_init_def_sb()
6037 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); in bnx2x_init_def_sb()
6245 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_internal_common()
6641 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
6642 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
6643 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
6644 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
6647 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
6686 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
6688 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
6696 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
6697 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
6698 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
6699 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
6702 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
6732 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); in bnx2x_int_mem_test()
6751 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
6753 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
6759 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_int_mem_test()
6762 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); in bnx2x_int_mem_test()
6763 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); in bnx2x_int_mem_test()
6764 REG_WR(bp, CFC_REG_DEBUG0, 0x0); in bnx2x_int_mem_test()
6765 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); in bnx2x_int_mem_test()
6776 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6778 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); in bnx2x_enable_blocks_attention()
6780 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6781 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6782 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6789 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); in bnx2x_enable_blocks_attention()
6790 REG_WR(bp, QM_REG_QM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6791 REG_WR(bp, TM_REG_TM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6792 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6793 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6794 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6797 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6798 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6799 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6802 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6803 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6804 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6805 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6815 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); in bnx2x_enable_blocks_attention()
6817 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6818 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6819 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6824 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); in bnx2x_enable_blocks_attention()
6826 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6827 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6829 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ in bnx2x_enable_blocks_attention()
6837 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_reset_common()
6845 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); in bnx2x_reset_common()
6914 REG_WR(bp, MISC_REG_SPIO_INT, val); in bnx2x_setup_fan_failure_detection()
6919 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); in bnx2x_setup_fan_failure_detection()
6927 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_pf_disable()
6928 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_pf_disable()
6929 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); in bnx2x_pf_disable()
6955 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); in bnx2x_config_endianity()
6956 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); in bnx2x_config_endianity()
6957 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); in bnx2x_config_endianity()
6958 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); in bnx2x_config_endianity()
6959 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); in bnx2x_config_endianity()
6962 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); in bnx2x_config_endianity()
6964 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); in bnx2x_config_endianity()
6965 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); in bnx2x_config_endianity()
6966 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); in bnx2x_config_endianity()
6967 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); in bnx2x_config_endianity()
7002 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); in bnx2x_init_hw_common()
7009 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); in bnx2x_init_hw_common()
7028 REG_WR(bp, in bnx2x_init_hw_common()
7045 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_init_hw_common()
7054 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); in bnx2x_init_hw_common()
7163 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); in bnx2x_init_hw_common()
7164 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); in bnx2x_init_hw_common()
7165 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); in bnx2x_init_hw_common()
7168 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
7169 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
7217 REG_WR(bp, QM_REG_SOFT_RESET, 1); in bnx2x_init_hw_common()
7218 REG_WR(bp, QM_REG_SOFT_RESET, 0); in bnx2x_init_hw_common()
7227 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_init_hw_common()
7232 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); in bnx2x_init_hw_common()
7235 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); in bnx2x_init_hw_common()
7242 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_common()
7243 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); in bnx2x_init_hw_common()
7244 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); in bnx2x_init_hw_common()
7245 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); in bnx2x_init_hw_common()
7246 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); in bnx2x_init_hw_common()
7251 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, in bnx2x_init_hw_common()
7263 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bnx2x_init_hw_common()
7266 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bnx2x_init_hw_common()
7279 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_init_hw_common()
7281 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, in bnx2x_init_hw_common()
7293 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_common()
7294 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); in bnx2x_init_hw_common()
7295 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); in bnx2x_init_hw_common()
7296 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); in bnx2x_init_hw_common()
7297 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); in bnx2x_init_hw_common()
7299 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, in bnx2x_init_hw_common()
7304 REG_WR(bp, SRC_REG_SOFT_RST, 1); in bnx2x_init_hw_common()
7309 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); in bnx2x_init_hw_common()
7310 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); in bnx2x_init_hw_common()
7311 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); in bnx2x_init_hw_common()
7312 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); in bnx2x_init_hw_common()
7313 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); in bnx2x_init_hw_common()
7314 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); in bnx2x_init_hw_common()
7315 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); in bnx2x_init_hw_common()
7316 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); in bnx2x_init_hw_common()
7317 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); in bnx2x_init_hw_common()
7318 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); in bnx2x_init_hw_common()
7320 REG_WR(bp, SRC_REG_SOFT_RST, 0); in bnx2x_init_hw_common()
7330 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); in bnx2x_init_hw_common()
7333 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); in bnx2x_init_hw_common()
7335 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_init_hw_common()
7338 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); in bnx2x_init_hw_common()
7343 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); in bnx2x_init_hw_common()
7349 REG_WR(bp, 0x2814, 0xffffffff); in bnx2x_init_hw_common()
7350 REG_WR(bp, 0x3820, 0xffffffff); in bnx2x_init_hw_common()
7353 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, in bnx2x_init_hw_common()
7356 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, in bnx2x_init_hw_common()
7360 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, in bnx2x_init_hw_common()
7370 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); in bnx2x_init_hw_common()
7374 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); in bnx2x_init_hw_common()
7395 REG_WR(bp, CFC_REG_DEBUG0, 0); in bnx2x_init_hw_common()
7455 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_init_hw_port()
7467 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_init_hw_port()
7484 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); in bnx2x_init_hw_port()
7485 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); in bnx2x_init_hw_port()
7508 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); in bnx2x_init_hw_port()
7509 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); in bnx2x_init_hw_port()
7513 REG_WR(bp, (BP_PORT(bp) ? in bnx2x_init_hw_port()
7521 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7524 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7527 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7535 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7559 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_init_hw_port()
7562 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); in bnx2x_init_hw_port()
7564 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); in bnx2x_init_hw_port()
7567 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); in bnx2x_init_hw_port()
7569 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); in bnx2x_init_hw_port()
7579 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
7580 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
7594 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); in bnx2x_init_hw_port()
7598 REG_WR(bp, reg, in bnx2x_init_hw_port()
7603 REG_WR(bp, reg, in bnx2x_init_hw_port()
7614 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7618 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7624 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7629 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bnx2x_init_hw_port()
7633 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, in bnx2x_init_hw_port()
7648 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : in bnx2x_init_hw_port()
7652 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); in bnx2x_init_hw_port()
7653 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); in bnx2x_init_hw_port()
7654 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); in bnx2x_init_hw_port()
7665 REG_WR(bp, reg_addr, val); in bnx2x_init_hw_port()
7711 REG_WR(bp, igu_addr_data, data); in bnx2x_igu_clear_sb_gen()
7716 REG_WR(bp, igu_addr_ctl, ctl); in bnx2x_igu_clear_sb_gen()
7748 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); in bnx2x_init_searcher()
7788 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7796 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + in bnx2x_reset_nic_mode()
7803 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : in bnx2x_reset_nic_mode()
7818 REG_WR(bp, PRS_REG_NIC_MODE, 0); in bnx2x_reset_nic_mode()
7824 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7827 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + in bnx2x_reset_nic_mode()
7835 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : in bnx2x_reset_nic_mode()
7879 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, in bnx2x_clean_pglue_errors()
7910 REG_WR(bp, addr, val); in bnx2x_init_hw_func()
7938 REG_WR(bp, PRS_REG_NIC_MODE, 0); in bnx2x_init_hw_func()
7942 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_init_hw_func()
7966 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_init_hw_func()
7968 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); in bnx2x_init_hw_func()
7992 REG_WR(bp, QM_REG_PF_EN, 1); in bnx2x_init_hw_func()
7995 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
7996 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
7997 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
7998 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8004 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ in bnx2x_init_hw_func()
8018 REG_WR(bp, PBF_REG_DISABLE_PF, 0); in bnx2x_init_hw_func()
8025 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); in bnx2x_init_hw_func()
8029 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); in bnx2x_init_hw_func()
8030 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, in bnx2x_init_hw_func()
8040 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
8042 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
8043 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
8050 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
8053 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
8054 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
8091 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
8121 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
8145 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in bnx2x_init_hw_func()
8146 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in bnx2x_init_hw_func()
8147 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); in bnx2x_init_hw_func()
8148 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); in bnx2x_init_hw_func()
8149 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); in bnx2x_init_hw_func()
8150 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); in bnx2x_init_hw_func()
8155 REG_WR(bp, 0x2114, 0xffffffff); in bnx2x_init_hw_func()
8156 REG_WR(bp, 0x2120, 0xffffffff); in bnx2x_init_hw_func()
8882 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), in bnx2x_reset_func()
8887 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
8888 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
8890 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_reset_func()
8891 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_reset_func()
8896 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); in bnx2x_reset_func()
8939 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_reset_port()
8942 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); in bnx2x_reset_port()
8944 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_reset_port()
8948 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); in bnx2x_reset_port()
9166 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_disable_ptp()
9170 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_disable_ptp()
9172 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_disable_ptp()
9174 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_disable_ptp()
9176 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_disable_ptp()
9180 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : in bnx2x_disable_ptp()
9241 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_chip_cleanup()
9361 REG_WR(bp, addr, val); in bnx2x_disable_close_the_gate()
9366 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); in bnx2x_disable_close_the_gate()
9378 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); in bnx2x_set_234_gates()
9380 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); in bnx2x_set_234_gates()
9387 REG_WR(bp, HC_REG_CONFIG_1, in bnx2x_set_234_gates()
9392 REG_WR(bp, HC_REG_CONFIG_0, in bnx2x_set_234_gates()
9399 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, in bnx2x_set_234_gates()
9460 REG_WR(bp, shmem + validity_offset, 0); in bnx2x_reset_mcp_prep()
9520 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); in bnx2x_pxp_prep()
9521 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); in bnx2x_pxp_prep()
9615 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_process_kill_chip_reset()
9618 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_process_kill_chip_reset()
9624 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_process_kill_chip_reset()
9630 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); in bnx2x_process_kill_chip_reset()
9712 REG_WR(bp, MISC_REG_UNPREPARED, 0); in bnx2x_process_kill()
9738 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); in bnx2x_process_kill()
10172 REG_WR(bp, vals->umac_addr[port], 0); in bnx2x_prev_unload_close_umac()
10212 REG_WR(bp, vals->bmac_addr, wb_data[0]); in bnx2x_prev_unload_close_mac()
10213 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); in bnx2x_prev_unload_close_mac()
10218 REG_WR(bp, vals->emac_addr, 0); in bnx2x_prev_unload_close_mac()
10225 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, in bnx2x_prev_unload_close_mac()
10227 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, in bnx2x_prev_unload_close_mac()
10231 REG_WR(bp, vals->xmac_addr, 0); in bnx2x_prev_unload_close_mac()
10288 REG_WR(bp, addr, tmp_reg); in bnx2x_prev_unload_undi_inc()
10544 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); in bnx2x_prev_unload_common()
10550 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_prev_unload_common()
10584 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); in bnx2x_prev_unload_common()
10586 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); in bnx2x_prev_unload_common()
10588 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); in bnx2x_prev_unload_common()
10590 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); in bnx2x_prev_unload_common()
10592 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); in bnx2x_prev_unload_common()
10593 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); in bnx2x_prev_unload_common()
10625 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, in bnx2x_prev_unload()
10630 REG_WR(bp, hw_lock_reg, 0xffffffff); in bnx2x_prev_unload()
11695 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); in bnx2x_get_hwinfo()
11696 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); in bnx2x_get_hwinfo()
12755 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); in bnx2x_init_dev()
12756 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); in bnx2x_init_dev()
12757 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); in bnx2x_init_dev()
12758 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); in bnx2x_init_dev()
12761 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); in bnx2x_init_dev()
12762 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); in bnx2x_init_dev()
12763 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); in bnx2x_init_dev()
12764 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); in bnx2x_init_dev()
12772 REG_WR(bp, in bnx2x_init_dev()
13945 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); in bnx2x_notify_link_changed()
14323 REG_WR(bp, scratch_offset + i, in bnx2x_drv_ctl()
14552 REG_WR(bp, pretend_reg, pretend_func_val); in bnx2x_pretend_func()
14576 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_ptp_task()
14607 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : in bnx2x_set_rx_ts()
14708 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
14710 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
14730 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
14732 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
14740 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
14742 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
14750 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
14752 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
14761 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
14763 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
14774 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_configure_ptp_filters()
14819 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp()
14821 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp()
14823 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_configure_ptp()
14825 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_configure_ptp()
14829 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_configure_ptp()
14833 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : in bnx2x_configure_ptp()
14849 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : in bnx2x_configure_ptp()
14851 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_configure_ptp()