1948 	u32 wb_data[2];  in bnx2x_update_pfc_bmac1()  local
1959 	wb_data[0] = val;  in bnx2x_update_pfc_bmac1()
1960 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac1()
1961 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac1()
1969 	wb_data[0] = val;  in bnx2x_update_pfc_bmac1()
1970 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac1()
1971 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac1()
1981 	u32 wb_data[2];  in bnx2x_update_pfc_bmac2()  local
1992 	wb_data[0] = val;  in bnx2x_update_pfc_bmac2()
1993 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
1994 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac2()
2003 	wb_data[0] = val;  in bnx2x_update_pfc_bmac2()
2004 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2005 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac2()
2010 		wb_data[0] = 0x0;  in bnx2x_update_pfc_bmac2()
2011 		wb_data[0] |= (1<<0);  /* RX */  in bnx2x_update_pfc_bmac2()
2012 		wb_data[0] |= (1<<1);  /* TX */  in bnx2x_update_pfc_bmac2()
2013 		wb_data[0] |= (1<<2);  /* Force initial Xon */  in bnx2x_update_pfc_bmac2()
2014 		wb_data[0] |= (1<<3);  /* 8 cos */  in bnx2x_update_pfc_bmac2()
2015 		wb_data[0] |= (1<<5);  /* STATS */  in bnx2x_update_pfc_bmac2()
2016 		wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2018 			    wb_data, 2);  in bnx2x_update_pfc_bmac2()
2020 		wb_data[0] &= ~(1<<2);  in bnx2x_update_pfc_bmac2()
2024 		wb_data[0] = 0x8;  in bnx2x_update_pfc_bmac2()
2025 		wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2028 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac2()
2039 	wb_data[0] = val;  in bnx2x_update_pfc_bmac2()
2040 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2042 		    wb_data, 2);  in bnx2x_update_pfc_bmac2()
2054 	wb_data[0] = val;  in bnx2x_update_pfc_bmac2()
2055 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2056 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac2()
2284 	u32 wb_data[2];  in bnx2x_bmac1_enable()  local
2290 	wb_data[0] = 0x3c;  in bnx2x_bmac1_enable()
2291 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2293 		    wb_data, 2);  in bnx2x_bmac1_enable()
2296 	wb_data[0] = ((params->mac_addr[2] << 24) |  in bnx2x_bmac1_enable()
2300 	wb_data[1] = ((params->mac_addr[0] << 8) |  in bnx2x_bmac1_enable()
2302 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);  in bnx2x_bmac1_enable()
2310 	wb_data[0] = val;  in bnx2x_bmac1_enable()
2311 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2312 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);  in bnx2x_bmac1_enable()
2315 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;  in bnx2x_bmac1_enable()
2316 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2317 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);  in bnx2x_bmac1_enable()
2322 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;  in bnx2x_bmac1_enable()
2323 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2324 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);  in bnx2x_bmac1_enable()
2327 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;  in bnx2x_bmac1_enable()
2328 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2329 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);  in bnx2x_bmac1_enable()
2332 	wb_data[0] = 0x1000200;  in bnx2x_bmac1_enable()
2333 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2335 		    wb_data, 2);  in bnx2x_bmac1_enable()
2348 	u32 wb_data[2];  in bnx2x_bmac2_enable()  local
2352 	wb_data[0] = 0;  in bnx2x_bmac2_enable()
2353 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2354 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);  in bnx2x_bmac2_enable()
2358 	wb_data[0] = 0x3c;  in bnx2x_bmac2_enable()
2359 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2361 		    wb_data, 2);  in bnx2x_bmac2_enable()
2366 	wb_data[0] = ((params->mac_addr[2] << 24) |  in bnx2x_bmac2_enable()
2370 	wb_data[1] = ((params->mac_addr[0] << 8) |  in bnx2x_bmac2_enable()
2373 		    wb_data, 2);  in bnx2x_bmac2_enable()
2378 	wb_data[0] = 0x1000200;  in bnx2x_bmac2_enable()
2379 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2381 		    wb_data, 2);  in bnx2x_bmac2_enable()
2385 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;  in bnx2x_bmac2_enable()
2386 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2387 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);  in bnx2x_bmac2_enable()
2391 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;  in bnx2x_bmac2_enable()
2392 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2393 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);  in bnx2x_bmac2_enable()
2396 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;  in bnx2x_bmac2_enable()
2397 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2398 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);  in bnx2x_bmac2_enable()
2454 	u32 wb_data[2];  in bnx2x_set_bmac_rx()  local
2466 		REG_RD_DMAE(bp, bmac_addr, wb_data, 2);  in bnx2x_set_bmac_rx()
2468 			wb_data[0] |= BMAC_CONTROL_RX_ENABLE;  in bnx2x_set_bmac_rx()
2470 			wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;  in bnx2x_set_bmac_rx()
2471 		REG_WR_DMAE(bp, bmac_addr, wb_data, 2);  in bnx2x_set_bmac_rx()
13480 		u32 wb_data[2];  in bnx2x_check_half_open_conn()  local
13489 		REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);  in bnx2x_check_half_open_conn()
13490 		lss_status = (wb_data[0] > 0);  in bnx2x_check_half_open_conn()