Lines Matching refs:umac_base
1536 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; in bnx2x_set_umac_rxtx() local
1542 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); in bnx2x_set_umac_rxtx()
1550 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_set_umac_rxtx()
1557 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; in bnx2x_umac_enable() local
1603 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1609 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, in bnx2x_umac_enable()
1611 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); in bnx2x_umac_enable()
1613 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); in bnx2x_umac_enable()
1617 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, in bnx2x_umac_enable()
1622 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, in bnx2x_umac_enable()
1630 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1639 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1644 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_umac_enable()
11166 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; in bnx2x_54618se_config_loopback() local
11198 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_54618se_config_loopback()