Lines Matching refs:phy
30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
221 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
1459 params->phy[phy_index].mdio_ctrl); in bnx2x_set_mdio_emac_per_phy()
1765 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { in bnx2x_xmac_enable()
1796 (params->phy[INT_PHY].supported & in bnx2x_xmac_enable()
2597 struct bnx2x_phy *phy, in bnx2x_cl22_write() argument
2604 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_write()
2605 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_write()
2609 tmp = ((phy->addr << 21) | (reg << 16) | val | in bnx2x_cl22_write()
2612 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl22_write()
2617 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_write()
2627 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_write()
2632 struct bnx2x_phy *phy, in bnx2x_cl22_read() argument
2640 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_read()
2641 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_read()
2645 val = ((phy->addr << 21) | (reg << 16) | in bnx2x_cl22_read()
2648 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl22_read()
2653 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_read()
2666 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_read()
2673 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_read() argument
2680 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { in bnx2x_cl45_read()
2683 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_read()
2686 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_read()
2687 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2690 val = ((phy->addr << 21) | (devad << 16) | reg | in bnx2x_cl45_read()
2693 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2698 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_read()
2711 val = ((phy->addr << 21) | (devad << 16) | in bnx2x_cl45_read()
2714 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2719 val = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_read()
2734 if (phy->flags & FLAGS_MDC_MDIO_WA) { in bnx2x_cl45_read()
2735 phy->flags ^= FLAGS_DUMMY_READ; in bnx2x_cl45_read()
2736 if (phy->flags & FLAGS_DUMMY_READ) { in bnx2x_cl45_read()
2738 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_read()
2742 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_read()
2743 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2748 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_write() argument
2755 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { in bnx2x_cl45_write()
2758 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_write()
2761 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_write()
2762 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2766 tmp = ((phy->addr << 21) | (devad << 16) | reg | in bnx2x_cl45_write()
2769 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2774 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_write()
2786 tmp = ((phy->addr << 21) | (devad << 16) | val | in bnx2x_cl45_write()
2789 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2794 tmp = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_write()
2808 if (phy->flags & FLAGS_MDC_MDIO_WA) { in bnx2x_cl45_write()
2809 phy->flags ^= FLAGS_DUMMY_READ; in bnx2x_cl45_write()
2810 if (phy->flags & FLAGS_DUMMY_READ) { in bnx2x_cl45_write()
2812 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_write()
2815 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_write()
2816 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2959 static int bnx2x_eee_disable(struct bnx2x_phy *phy, in bnx2x_eee_disable() argument
2968 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); in bnx2x_eee_disable()
2975 static int bnx2x_eee_advertise(struct bnx2x_phy *phy, in bnx2x_eee_advertise() argument
2994 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); in bnx2x_eee_advertise()
3012 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, in bnx2x_eee_an_resolve() argument
3021 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); in bnx2x_eee_an_resolve()
3022 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); in bnx2x_eee_an_resolve()
3175 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_read_or_write() argument
3179 bnx2x_cl45_read(bp, phy, devad, reg, &val); in bnx2x_cl45_read_or_write()
3180 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); in bnx2x_cl45_read_or_write()
3184 struct bnx2x_phy *phy, in bnx2x_cl45_read_and_write() argument
3188 bnx2x_cl45_read(bp, phy, devad, reg, &val); in bnx2x_cl45_read_and_write()
3189 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); in bnx2x_cl45_read_and_write()
3200 if (params->phy[phy_index].addr == phy_addr) { in bnx2x_phy_read()
3202 ¶ms->phy[phy_index], devad, in bnx2x_phy_read()
3217 if (params->phy[phy_index].addr == phy_addr) { in bnx2x_phy_write()
3219 ¶ms->phy[phy_index], devad, in bnx2x_phy_write()
3225 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, in bnx2x_get_warpcore_lane() argument
3280 struct bnx2x_phy *phy) in bnx2x_set_aer_mmd() argument
3289 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? in bnx2x_set_aer_mmd()
3290 (phy->addr + ser_lane) : 0; in bnx2x_set_aer_mmd()
3293 aer_val = bnx2x_get_warpcore_lane(phy, params); in bnx2x_set_aer_mmd()
3300 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_set_aer_mmd()
3307 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_set_aer_mmd()
3349 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, in bnx2x_xgxs_specific_func() argument
3359 phy->def_md_devad); in bnx2x_xgxs_specific_func()
3378 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, in bnx2x_xgxs_deassert()
3382 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, in bnx2x_calc_ieee_aneg_adv() argument
3391 switch (phy->req_flow_ctrl) { in bnx2x_calc_ieee_aneg_adv()
3440 params->phy[actual_phy_idx].req_flow_ctrl = in set_phy_vars()
3443 params->phy[actual_phy_idx].req_line_speed = in set_phy_vars()
3446 params->phy[actual_phy_idx].speed_cap_mask = in set_phy_vars()
3449 params->phy[actual_phy_idx].req_duplex = in set_phy_vars()
3458 params->phy[actual_phy_idx].req_flow_ctrl, in set_phy_vars()
3459 params->phy[actual_phy_idx].req_line_speed, in set_phy_vars()
3460 params->phy[actual_phy_idx].speed_cap_mask); in set_phy_vars()
3465 struct bnx2x_phy *phy, in bnx2x_ext_phy_set_pause() argument
3471 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); in bnx2x_ext_phy_set_pause()
3476 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_ext_phy_set_pause()
3488 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); in bnx2x_ext_phy_set_pause()
3519 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, in bnx2x_ext_phy_update_adv_fc() argument
3527 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { in bnx2x_ext_phy_update_adv_fc()
3528 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); in bnx2x_ext_phy_update_adv_fc()
3529 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); in bnx2x_ext_phy_update_adv_fc()
3532 u8 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_ext_phy_update_adv_fc()
3534 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3541 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3543 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3546 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3548 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3558 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3561 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3574 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, in bnx2x_ext_phy_resolve_fc() argument
3580 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { in bnx2x_ext_phy_resolve_fc()
3582 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_ext_phy_resolve_fc()
3583 bnx2x_ext_phy_update_adv_fc(phy, params, vars); in bnx2x_ext_phy_resolve_fc()
3585 vars->flow_ctrl = phy->req_flow_ctrl; in bnx2x_ext_phy_resolve_fc()
3586 } else if (phy->req_line_speed != SPEED_AUTO_NEG) in bnx2x_ext_phy_resolve_fc()
3590 bnx2x_ext_phy_update_adv_fc(phy, params, vars); in bnx2x_ext_phy_resolve_fc()
3613 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, in bnx2x_warpcore_enable_AN_KR2() argument
3640 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR2()
3644 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR2()
3654 struct bnx2x_phy *phy) in bnx2x_disable_kr2() argument
3679 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_disable_kr2()
3687 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, in bnx2x_warpcore_set_lpi_passthrough() argument
3693 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_lpi_passthrough()
3695 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_lpi_passthrough()
3699 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy, in bnx2x_warpcore_restart_AN_KR() argument
3704 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_restart_AN_KR()
3705 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_restart_AN_KR()
3707 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_restart_AN_KR()
3711 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_restart_AN_KR()
3714 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, in bnx2x_warpcore_enable_AN_KR() argument
3733 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR()
3736 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3740 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3745 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || in bnx2x_warpcore_enable_AN_KR()
3751 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); in bnx2x_warpcore_enable_AN_KR()
3755 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || in bnx2x_warpcore_enable_AN_KR()
3760 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_enable_AN_KR()
3763 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3765 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_enable_AN_KR()
3770 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_enable_AN_KR()
3771 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3775 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_warpcore_enable_AN_KR()
3776 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3779 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3782 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3787 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3791 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3801 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3808 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_warpcore_enable_AN_KR()
3810 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3814 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3817 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_warpcore_enable_AN_KR()
3818 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || in bnx2x_warpcore_enable_AN_KR()
3819 (phy->req_line_speed == SPEED_20000)) { in bnx2x_warpcore_enable_AN_KR()
3821 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_enable_AN_KR()
3824 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3828 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3830 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_enable_AN_KR()
3832 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); in bnx2x_warpcore_enable_AN_KR()
3835 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3840 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3855 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3859 bnx2x_disable_kr2(params, vars, phy); in bnx2x_warpcore_enable_AN_KR()
3863 bnx2x_warpcore_restart_AN_KR(phy, params); in bnx2x_warpcore_enable_AN_KR()
3866 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, in bnx2x_warpcore_set_10G_KR() argument
3886 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_set_10G_KR()
3889 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_set_10G_KR()
3891 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_10G_KR()
3894 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3897 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3900 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3903 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3906 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_set_10G_KR()
3908 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_10G_KR()
3911 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_10G_KR()
3915 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3919 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3923 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3927 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3929 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3934 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, in bnx2x_warpcore_set_10G_XFI() argument
3944 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3948 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3952 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); in bnx2x_warpcore_set_10G_XFI()
3955 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3959 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3963 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3967 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3972 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3974 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3979 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4035 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4039 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_set_10G_XFI()
4040 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4043 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4048 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4052 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4055 bnx2x_warpcore_set_lpi_passthrough(phy, params); in bnx2x_warpcore_set_10G_XFI()
4058 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4062 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4066 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4070 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, in bnx2x_warpcore_set_20G_force_KR2() argument
4076 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_20G_force_KR2()
4080 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4083 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_set_20G_force_KR2()
4085 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4087 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4090 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4094 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4098 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4101 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4104 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4108 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4110 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4114 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_20G_force_KR2()
4117 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4120 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_set_20G_force_KR2()
4124 struct bnx2x_phy *phy, in bnx2x_warpcore_set_20G_DXGXS() argument
4128 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4132 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4135 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4138 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4141 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4144 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4147 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4150 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4153 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4156 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4160 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4164 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4168 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4172 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4177 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, in bnx2x_warpcore_set_sgmii_speed() argument
4186 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4189 bnx2x_warpcore_set_lpi_passthrough(phy, params); in bnx2x_warpcore_set_sgmii_speed()
4191 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_warpcore_set_sgmii_speed()
4193 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4198 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4201 switch (phy->req_line_speed) { in bnx2x_warpcore_set_sgmii_speed()
4212 "Speed not supported: 0x%x\n", phy->req_line_speed); in bnx2x_warpcore_set_sgmii_speed()
4216 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_warpcore_set_sgmii_speed()
4219 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4223 phy->req_line_speed); in bnx2x_warpcore_set_sgmii_speed()
4224 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4230 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4237 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4242 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4244 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4249 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4254 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4260 struct bnx2x_phy *phy, in bnx2x_warpcore_reset_lane() argument
4265 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4271 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4273 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4277 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, in bnx2x_warpcore_clear_regs() argument
4300 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_clear_regs()
4304 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, in bnx2x_warpcore_clear_regs()
4307 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_clear_regs()
4308 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_clear_regs()
4352 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, in bnx2x_is_sfp_module_plugged() argument
4370 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, in bnx2x_warpcore_get_sigdet() argument
4376 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_get_sigdet()
4378 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, in bnx2x_warpcore_get_sigdet()
4384 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, in bnx2x_warpcore_config_runtime() argument
4398 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_config_runtime()
4407 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, in bnx2x_warpcore_config_runtime()
4417 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_config_runtime()
4418 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_runtime()
4421 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_config_runtime()
4437 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, in bnx2x_warpcore_config_sfi() argument
4440 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_config_sfi()
4442 bnx2x_warpcore_clear_regs(phy, params, lane); in bnx2x_warpcore_config_sfi()
4445 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { in bnx2x_warpcore_config_sfi()
4447 bnx2x_warpcore_set_10G_XFI(phy, params, 0); in bnx2x_warpcore_config_sfi()
4450 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); in bnx2x_warpcore_config_sfi()
4455 struct bnx2x_phy *phy, in bnx2x_sfp_e3_set_transmitter() argument
4471 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) in bnx2x_sfp_e3_set_transmitter()
4475 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, in bnx2x_warpcore_config_init() argument
4482 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_config_init()
4490 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_config_init()
4491 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_config_init()
4494 (phy->req_line_speed && in bnx2x_warpcore_config_init()
4495 ((phy->req_line_speed == SPEED_100) || in bnx2x_warpcore_config_init()
4496 (phy->req_line_speed == SPEED_10)))) { in bnx2x_warpcore_config_init()
4499 bnx2x_warpcore_clear_regs(phy, params, lane); in bnx2x_warpcore_config_init()
4500 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); in bnx2x_warpcore_config_init()
4506 bnx2x_warpcore_enable_AN_KR(phy, params, vars); in bnx2x_warpcore_config_init()
4509 bnx2x_warpcore_set_10G_KR(phy, params, vars); in bnx2x_warpcore_config_init()
4514 bnx2x_warpcore_clear_regs(phy, params, lane); in bnx2x_warpcore_config_init()
4517 bnx2x_warpcore_set_10G_XFI(phy, params, 1); in bnx2x_warpcore_config_init()
4526 bnx2x_warpcore_set_sgmii_speed(phy, in bnx2x_warpcore_config_init()
4541 if (bnx2x_is_sfp_module_plugged(phy, params)) in bnx2x_warpcore_config_init()
4542 bnx2x_sfp_module_detection(phy, params); in bnx2x_warpcore_config_init()
4545 phy, 1); in bnx2x_warpcore_config_init()
4548 bnx2x_warpcore_config_sfi(phy, params); in bnx2x_warpcore_config_init()
4557 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); in bnx2x_warpcore_config_init()
4560 bnx2x_sfp_module_detection(phy, params); in bnx2x_warpcore_config_init()
4564 bnx2x_warpcore_enable_AN_KR(phy, params, vars); in bnx2x_warpcore_config_init()
4567 bnx2x_warpcore_set_20G_force_KR2(phy, params); in bnx2x_warpcore_config_init()
4579 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_init()
4583 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, in bnx2x_warpcore_link_reset() argument
4588 bnx2x_sfp_e3_set_transmitter(params, phy, 0); in bnx2x_warpcore_link_reset()
4590 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_link_reset()
4592 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_link_reset()
4596 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4599 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4603 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_link_reset()
4606 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4610 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4612 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_link_reset()
4614 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4617 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_warpcore_link_reset()
4619 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4622 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4626 if (phy->flags & FLAGS_WC_DUAL_MODE) { in bnx2x_warpcore_link_reset()
4631 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4634 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_link_reset()
4638 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, in bnx2x_set_warpcore_loopback() argument
4645 params->loopback_mode, phy->req_line_speed); in bnx2x_set_warpcore_loopback()
4647 if (phy->req_line_speed < SPEED_10000 || in bnx2x_set_warpcore_loopback()
4648 phy->supported & SUPPORTED_20000baseKR2_Full) { in bnx2x_set_warpcore_loopback()
4652 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_set_warpcore_loopback()
4655 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4659 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_set_warpcore_loopback()
4660 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4663 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_set_warpcore_loopback()
4665 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4670 bnx2x_set_aer_mmd(params, phy); in bnx2x_set_warpcore_loopback()
4673 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4676 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4820 params->phy[INT_PHY].media_type = in bnx2x_link_status_update()
4823 params->phy[EXT_PHY1].media_type = in bnx2x_link_status_update()
4826 params->phy[EXT_PHY2].media_type = in bnx2x_link_status_update()
4857 struct bnx2x_phy *phy) in bnx2x_set_master_ln() argument
4866 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_master_ln()
4871 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_master_ln()
4878 struct bnx2x_phy *phy, in bnx2x_reset_unicore() argument
4884 CL22_RD_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4889 CL22_WR_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4902 CL22_RD_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4922 struct bnx2x_phy *phy) in bnx2x_set_swap_lanes() argument
4938 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4945 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4951 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4957 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4963 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, in bnx2x_set_parallel_detection() argument
4968 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4972 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) in bnx2x_set_parallel_detection()
4977 phy->speed_cap_mask, control2); in bnx2x_set_parallel_detection()
4978 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4983 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && in bnx2x_set_parallel_detection()
4984 (phy->speed_cap_mask & in bnx2x_set_parallel_detection()
4988 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4993 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5002 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5008 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5016 static void bnx2x_set_autoneg(struct bnx2x_phy *phy, in bnx2x_set_autoneg() argument
5025 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5036 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5042 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5053 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5058 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5071 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5078 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5084 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5092 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5096 if (phy->speed_cap_mask & in bnx2x_set_autoneg()
5099 if (phy->speed_cap_mask & in bnx2x_set_autoneg()
5103 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5114 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5120 static void bnx2x_program_serdes(struct bnx2x_phy *phy, in bnx2x_program_serdes() argument
5128 CL22_RD_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5134 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_program_serdes()
5136 CL22_WR_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5143 CL22_RD_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5163 CL22_WR_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5169 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, in bnx2x_set_brcm_cl37_advertisement() argument
5176 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) in bnx2x_set_brcm_cl37_advertisement()
5178 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) in bnx2x_set_brcm_cl37_advertisement()
5180 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_brcm_cl37_advertisement()
5184 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_brcm_cl37_advertisement()
5189 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, in bnx2x_set_ieee_aneg_advertisement() argument
5197 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5200 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5205 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5210 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, in bnx2x_restart_autoneg() argument
5221 CL22_RD_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5226 CL22_WR_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5234 CL22_RD_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5241 CL22_WR_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5250 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, in bnx2x_initialize_sgmii_process() argument
5259 CL22_RD_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5268 CL22_WR_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5278 CL22_RD_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5306 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_initialize_sgmii_process()
5309 CL22_WR_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5316 bnx2x_restart_autoneg(phy, params, 0); in bnx2x_initialize_sgmii_process()
5322 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, in bnx2x_direct_parallel_detect_used() argument
5327 if (phy->req_line_speed != SPEED_AUTO_NEG) in bnx2x_direct_parallel_detect_used()
5329 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5333 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5343 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5356 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, in bnx2x_update_adv_fc() argument
5371 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5375 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5385 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5389 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5403 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, in bnx2x_flow_ctrl_resolve() argument
5412 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { in bnx2x_flow_ctrl_resolve()
5414 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_flow_ctrl_resolve()
5415 bnx2x_update_adv_fc(phy, params, vars, gp_status); in bnx2x_flow_ctrl_resolve()
5417 vars->flow_ctrl = phy->req_flow_ctrl; in bnx2x_flow_ctrl_resolve()
5418 } else if (phy->req_line_speed != SPEED_AUTO_NEG) in bnx2x_flow_ctrl_resolve()
5422 if (bnx2x_direct_parallel_detect_used(phy, params)) { in bnx2x_flow_ctrl_resolve()
5426 bnx2x_update_adv_fc(phy, params, vars, gp_status); in bnx2x_flow_ctrl_resolve()
5431 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, in bnx2x_check_fallback_to_cl37() argument
5438 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5446 CL22_WR_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5453 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5469 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5490 CL22_WR_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5495 bnx2x_restart_autoneg(phy, params, 0); in bnx2x_check_fallback_to_cl37()
5499 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, in bnx2x_xgxs_an_resolve() argument
5508 if (bnx2x_direct_parallel_detect_used(phy, params)) in bnx2x_xgxs_an_resolve()
5512 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, in bnx2x_get_link_speed_duplex() argument
5520 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_get_link_speed_duplex()
5603 static int bnx2x_link_settings_status(struct bnx2x_phy *phy, in bnx2x_link_settings_status() argument
5613 CL22_RD_OVER_CL45(bp, phy, in bnx2x_link_settings_status()
5624 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, in bnx2x_link_settings_status()
5632 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); in bnx2x_link_settings_status()
5633 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_link_settings_status()
5634 bnx2x_xgxs_an_resolve(phy, params, vars, in bnx2x_link_settings_status()
5638 if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_link_settings_status()
5641 bnx2x_check_fallback_to_cl37(phy, params); in bnx2x_link_settings_status()
5650 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, in bnx2x_link_settings_status()
5661 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, in bnx2x_link_settings_status()
5677 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, in bnx2x_warpcore_read_status() argument
5685 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_read_status()
5688 (phy->flags & FLAGS_WC_DUAL_MODE)) { in bnx2x_warpcore_read_status()
5689 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5691 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5694 } else if ((phy->req_line_speed > SPEED_10000) && in bnx2x_warpcore_read_status()
5695 (phy->supported & SUPPORTED_20000baseMLD2_Full)) { in bnx2x_warpcore_read_status()
5697 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5699 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5705 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_warpcore_read_status()
5707 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5716 if (phy->supported & SUPPORTED_20000baseKR2_Full) { in bnx2x_warpcore_read_status()
5718 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5720 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5726 if (phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_warpcore_read_status()
5728 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5736 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5743 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_warpcore_read_status()
5752 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5763 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5777 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5780 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5790 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, in bnx2x_warpcore_read_status()
5794 if ((!link_up) && (phy->media_type == ETH_PHY_KR) && in bnx2x_warpcore_read_status()
5795 (!(phy->flags & FLAGS_WC_DUAL_MODE))) in bnx2x_warpcore_read_status()
5805 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; in bnx2x_set_gmii_tx_driver() local
5811 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5825 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5834 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5888 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, in bnx2x_set_preemphasis() argument
5897 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_preemphasis()
5900 phy->rx_preemphasis[i]); in bnx2x_set_preemphasis()
5905 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_preemphasis()
5908 phy->tx_preemphasis[i]); in bnx2x_set_preemphasis()
5912 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, in bnx2x_xgxs_config_init() argument
5923 bnx2x_set_preemphasis(phy, params); in bnx2x_xgxs_config_init()
5932 bnx2x_set_autoneg(phy, params, vars, 0); in bnx2x_xgxs_config_init()
5935 bnx2x_program_serdes(phy, params, vars); in bnx2x_xgxs_config_init()
5941 bnx2x_set_brcm_cl37_advertisement(phy, params); in bnx2x_xgxs_config_init()
5944 bnx2x_set_ieee_aneg_advertisement(phy, params, in bnx2x_xgxs_config_init()
5948 bnx2x_set_autoneg(phy, params, vars, enable_cl73); in bnx2x_xgxs_config_init()
5951 bnx2x_restart_autoneg(phy, params, enable_cl73); in bnx2x_xgxs_config_init()
5957 bnx2x_initialize_sgmii_process(phy, params, vars); in bnx2x_xgxs_config_init()
5961 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, in bnx2x_prepare_xgxs() argument
5967 if ((phy->req_line_speed && in bnx2x_prepare_xgxs()
5968 ((phy->req_line_speed == SPEED_100) || in bnx2x_prepare_xgxs()
5969 (phy->req_line_speed == SPEED_10))) || in bnx2x_prepare_xgxs()
5970 (!phy->req_line_speed && in bnx2x_prepare_xgxs()
5971 (phy->speed_cap_mask >= in bnx2x_prepare_xgxs()
5973 (phy->speed_cap_mask < in bnx2x_prepare_xgxs()
5975 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) in bnx2x_prepare_xgxs()
5980 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_prepare_xgxs()
5981 bnx2x_set_aer_mmd(params, phy); in bnx2x_prepare_xgxs()
5982 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in bnx2x_prepare_xgxs()
5983 bnx2x_set_master_ln(params, phy); in bnx2x_prepare_xgxs()
5985 rc = bnx2x_reset_unicore(params, phy, 0); in bnx2x_prepare_xgxs()
5990 bnx2x_set_aer_mmd(params, phy); in bnx2x_prepare_xgxs()
5992 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { in bnx2x_prepare_xgxs()
5993 bnx2x_set_master_ln(params, phy); in bnx2x_prepare_xgxs()
5994 bnx2x_set_swap_lanes(params, phy); in bnx2x_prepare_xgxs()
6001 struct bnx2x_phy *phy, in bnx2x_wait_reset_complete() argument
6007 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) in bnx2x_wait_reset_complete()
6008 bnx2x_cl22_read(bp, phy, in bnx2x_wait_reset_complete()
6011 bnx2x_cl45_read(bp, phy, in bnx2x_wait_reset_complete()
6043 params->phy[INT_PHY].type != in bnx2x_link_int_enable()
6053 params->phy[INT_PHY].type != in bnx2x_link_int_enable()
6209 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); in bnx2x_get_ext_phy_fw_version()
6211 if (params->phy[EXT_PHY1].format_fw_ver) { in bnx2x_get_ext_phy_fw_version()
6212 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, in bnx2x_get_ext_phy_fw_version()
6218 (params->phy[EXT_PHY2].ver_addr != 0)) { in bnx2x_get_ext_phy_fw_version()
6219 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); in bnx2x_get_ext_phy_fw_version()
6220 if (params->phy[EXT_PHY2].format_fw_ver) { in bnx2x_get_ext_phy_fw_version()
6224 status |= params->phy[EXT_PHY2].format_fw_ver( in bnx2x_get_ext_phy_fw_version()
6235 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, in bnx2x_set_xgxs_loopback() argument
6241 if (phy->req_line_speed != SPEED_1000) { in bnx2x_set_xgxs_loopback()
6255 bnx2x_cl45_write(bp, phy, in bnx2x_set_xgxs_loopback()
6261 bnx2x_cl45_write(bp, phy, in bnx2x_set_xgxs_loopback()
6268 bnx2x_set_aer_mmd(params, phy); in bnx2x_set_xgxs_loopback()
6278 bnx2x_cl45_read(bp, phy, 5, in bnx2x_set_xgxs_loopback()
6282 bnx2x_cl45_write(bp, phy, 5, in bnx2x_set_xgxs_loopback()
6305 if (params->phy[phy_idx].set_link_led) { in bnx2x_set_led()
6306 params->phy[phy_idx].set_link_led( in bnx2x_set_led()
6307 ¶ms->phy[phy_idx], params, mode); in bnx2x_set_led()
6319 if (params->phy[EXT_PHY1].type == in bnx2x_set_led()
6337 if (((params->phy[EXT_PHY1].type == in bnx2x_set_led()
6339 (params->phy[EXT_PHY1].type == in bnx2x_set_led()
6375 } else if ((params->phy[EXT_PHY1].type == in bnx2x_set_led()
6445 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; in bnx2x_test_link()
6487 ext_phy_link_up = params->phy[EXT_PHY1].read_status( in bnx2x_test_link()
6488 ¶ms->phy[EXT_PHY1], in bnx2x_test_link()
6494 serdes_phy_type = ((params->phy[phy_index].media_type == in bnx2x_test_link()
6496 (params->phy[phy_index].media_type == in bnx2x_test_link()
6498 (params->phy[phy_index].media_type == in bnx2x_test_link()
6500 (params->phy[phy_index].media_type == in bnx2x_test_link()
6505 if (params->phy[phy_index].read_status) { in bnx2x_test_link()
6507 params->phy[phy_index].read_status( in bnx2x_test_link()
6508 ¶ms->phy[phy_index], in bnx2x_test_link()
6529 vars->line_speed = params->phy[INT_PHY].req_line_speed; in bnx2x_link_initialize()
6536 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); in bnx2x_link_initialize()
6542 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || in bnx2x_link_initialize()
6544 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; in bnx2x_link_initialize() local
6548 bnx2x_set_parallel_detection(phy, params); in bnx2x_link_initialize()
6549 if (params->phy[INT_PHY].config_init) in bnx2x_link_initialize()
6550 params->phy[INT_PHY].config_init(phy, params, vars); in bnx2x_link_initialize()
6556 vars->line_speed = params->phy[INT_PHY].req_line_speed; in bnx2x_link_initialize()
6560 if (params->phy[INT_PHY].supported & in bnx2x_link_initialize()
6571 if (params->phy[phy_index].supported & in bnx2x_link_initialize()
6582 params->phy[phy_index].config_init( in bnx2x_link_initialize()
6583 ¶ms->phy[phy_index], in bnx2x_link_initialize()
6597 static void bnx2x_int_link_reset(struct bnx2x_phy *phy, in bnx2x_int_link_reset() argument
6605 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, in bnx2x_common_ext_link_reset() argument
6753 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { in bnx2x_update_link_up()
6820 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); in bnx2x_link_update()
6850 struct bnx2x_phy *phy = ¶ms->phy[phy_index]; in bnx2x_link_update() local
6851 if (!phy->read_status) in bnx2x_link_update()
6854 cur_link_up = phy->read_status(phy, params, in bnx2x_link_update()
6908 if (params->phy[INT_PHY].read_status) in bnx2x_link_update()
6909 params->phy[INT_PHY].read_status( in bnx2x_link_update()
6910 ¶ms->phy[INT_PHY], in bnx2x_link_update()
6930 if (params->phy[EXT_PHY2].phy_specific_func) { in bnx2x_link_update()
6933 params->phy[EXT_PHY2].phy_specific_func( in bnx2x_link_update()
6934 ¶ms->phy[EXT_PHY2], in bnx2x_link_update()
6941 if (params->phy[active_external_phy].supported & in bnx2x_link_update()
6955 if (params->phy[phy_index].flags & in bnx2x_link_update()
7002 params->phy[EXT_PHY1].flags & in bnx2x_link_update()
7004 if (!(params->phy[EXT_PHY1].flags & in bnx2x_link_update()
7013 if (params->phy[INT_PHY].config_init) in bnx2x_link_update()
7014 params->phy[INT_PHY].config_init( in bnx2x_link_update()
7015 ¶ms->phy[INT_PHY], params, in bnx2x_link_update()
7071 struct bnx2x_phy *phy, in bnx2x_save_bcm_spirom_ver() argument
7076 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_save_bcm_spirom_ver()
7078 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_save_bcm_spirom_ver()
7081 phy->ver_addr); in bnx2x_save_bcm_spirom_ver()
7085 struct bnx2x_phy *phy, in bnx2x_ext_phy_10G_an_resolve() argument
7089 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_10G_an_resolve()
7092 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_10G_an_resolve()
7104 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, in bnx2x_8073_resolve_fc() argument
7109 if (phy->req_line_speed == SPEED_10 || in bnx2x_8073_resolve_fc()
7110 phy->req_line_speed == SPEED_100) { in bnx2x_8073_resolve_fc()
7111 vars->flow_ctrl = phy->req_flow_ctrl; in bnx2x_8073_resolve_fc()
7115 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && in bnx2x_8073_resolve_fc()
7120 bnx2x_cl45_read(bp, phy, in bnx2x_8073_resolve_fc()
7124 bnx2x_cl45_read(bp, phy, in bnx2x_8073_resolve_fc()
7138 struct bnx2x_phy *phy, in bnx2x_8073_8727_external_rom_boot() argument
7147 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7153 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7158 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7163 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7169 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7189 bnx2x_cl45_read(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7192 bnx2x_cl45_read(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7198 ((fw_msgout & 0xff) != 0x03 && (phy->type == in bnx2x_8073_8727_external_rom_boot()
7202 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7205 bnx2x_save_bcm_spirom_ver(bp, phy, port); in bnx2x_8073_8727_external_rom_boot()
7218 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_8073_is_snr_needed() argument
7224 bnx2x_cl45_read(bp, phy, in bnx2x_8073_is_snr_needed()
7233 bnx2x_cl45_read(bp, phy, in bnx2x_8073_is_snr_needed()
7244 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_8073_xaui_wa() argument
7248 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7263 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7282 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7300 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_807x_force_10G() argument
7303 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7305 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7307 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7309 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7314 struct bnx2x_phy *phy, in bnx2x_8073_set_pause_cl37() argument
7319 bnx2x_cl45_read(bp, phy, in bnx2x_8073_set_pause_cl37()
7324 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_8073_set_pause_cl37()
7343 bnx2x_cl45_write(bp, phy, in bnx2x_8073_set_pause_cl37()
7348 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, in bnx2x_8073_specific_func() argument
7356 bnx2x_cl45_write(bp, phy, in bnx2x_8073_specific_func()
7358 bnx2x_cl45_write(bp, phy, in bnx2x_8073_specific_func()
7364 static int bnx2x_8073_config_init(struct bnx2x_phy *phy, in bnx2x_8073_config_init() argument
7384 bnx2x_8073_specific_func(phy, params, PHY_INIT); in bnx2x_8073_config_init()
7385 bnx2x_8073_set_pause_cl37(params, phy, vars); in bnx2x_8073_config_init()
7387 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7390 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7400 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7403 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7416 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7419 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7425 bnx2x_807x_force_10G(bp, phy); in bnx2x_8073_config_init()
7429 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7432 if (phy->req_line_speed != SPEED_AUTO_NEG) { in bnx2x_8073_config_init()
7433 if (phy->req_line_speed == SPEED_10000) { in bnx2x_8073_config_init()
7435 } else if (phy->req_line_speed == SPEED_2500) { in bnx2x_8073_config_init()
7444 if (phy->speed_cap_mask & in bnx2x_8073_config_init()
7449 if (phy->speed_cap_mask & in bnx2x_8073_config_init()
7456 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); in bnx2x_8073_config_init()
7457 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); in bnx2x_8073_config_init()
7459 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && in bnx2x_8073_config_init()
7460 (phy->req_line_speed == SPEED_AUTO_NEG)) || in bnx2x_8073_config_init()
7461 (phy->req_line_speed == SPEED_2500)) { in bnx2x_8073_config_init()
7464 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7477 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); in bnx2x_8073_config_init()
7480 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); in bnx2x_8073_config_init()
7481 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, in bnx2x_8073_config_init()
7482 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? in bnx2x_8073_config_init()
7486 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); in bnx2x_8073_config_init()
7492 if (bnx2x_8073_is_snr_needed(bp, phy)) in bnx2x_8073_config_init()
7493 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7498 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); in bnx2x_8073_config_init()
7500 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); in bnx2x_8073_config_init()
7502 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_8073_config_init()
7506 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in bnx2x_8073_config_init()
7512 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, in bnx2x_8073_read_status() argument
7522 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7528 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7530 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7534 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7538 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7544 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7548 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7550 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7556 ((phy->req_line_speed != SPEED_10000))) { in bnx2x_8073_read_status()
7557 if (bnx2x_8073_xaui_wa(bp, phy) != 0) in bnx2x_8073_read_status()
7560 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7562 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7566 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7568 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7574 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { in bnx2x_8073_read_status()
7579 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7584 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7588 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7619 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7632 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7637 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_8073_read_status()
7638 bnx2x_8073_resolve_fc(phy, params, vars); in bnx2x_8073_read_status()
7643 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_8073_read_status()
7657 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, in bnx2x_8073_link_reset() argument
7676 static int bnx2x_8705_config_init(struct bnx2x_phy *phy, in bnx2x_8705_config_init() argument
7687 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8705_config_init()
7688 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8705_config_init()
7690 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7692 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7694 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7696 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7703 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, in bnx2x_8705_read_status() argument
7711 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7715 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7719 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7722 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7724 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7731 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_8705_read_status()
7740 struct bnx2x_phy *phy, in bnx2x_set_disable_pmd_transmit() argument
7757 bnx2x_cl45_write(bp, phy, in bnx2x_set_disable_pmd_transmit()
7777 struct bnx2x_phy *phy, in bnx2x_sfp_e1e2_set_transmitter() argument
7795 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_e1e2_set_transmitter()
7805 bnx2x_cl45_write(bp, phy, in bnx2x_sfp_e1e2_set_transmitter()
7834 struct bnx2x_phy *phy, in bnx2x_sfp_set_transmitter() argument
7840 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); in bnx2x_sfp_set_transmitter()
7842 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); in bnx2x_sfp_set_transmitter()
7845 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, in bnx2x_8726_read_sfp_module_eeprom() argument
7859 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7864 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7869 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7875 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7894 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7901 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7933 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, in bnx2x_warpcore_read_sfp_module_eeprom() argument
7974 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, in bnx2x_8727_read_sfp_module_eeprom() argument
7992 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7998 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8004 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8010 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8015 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8021 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8032 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8051 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8058 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8069 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, in bnx2x_read_sfp_module_eeprom() argument
8084 switch (phy->type) { in bnx2x_read_sfp_module_eeprom()
8102 rc = read_func(phy, params, dev_addr, addr, xfer_size, in bnx2x_read_sfp_module_eeprom()
8111 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, in bnx2x_get_edc_mode() argument
8119 phy->media_type = ETH_PHY_UNSPECIFIED; in bnx2x_get_edc_mode()
8121 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_get_edc_mode()
8138 phy->media_type = ETH_PHY_DA_TWINAX; in bnx2x_get_edc_mode()
8147 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in bnx2x_get_edc_mode()
8178 phy->media_type = ETH_PHY_SFP_1G_FIBER; in bnx2x_get_edc_mode()
8179 if (phy->req_line_speed != SPEED_1000) { in bnx2x_get_edc_mode()
8181 phy->req_line_speed = SPEED_1000; in bnx2x_get_edc_mode()
8192 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_get_edc_mode()
8194 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_get_edc_mode()
8200 if (params->phy[idx].type == phy->type) { in bnx2x_get_edc_mode()
8205 phy->media_type = ETH_PHY_SFPP_10G_FIBER; in bnx2x_get_edc_mode()
8206 phy->req_line_speed = params->req_line_speed[cfg_idx]; in bnx2x_get_edc_mode()
8220 if (&(params->phy[phy_idx]) == phy) { in bnx2x_get_edc_mode()
8223 media_types |= ((phy->media_type & in bnx2x_get_edc_mode()
8232 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_get_edc_mode()
8253 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, in bnx2x_verify_sfp_module() argument
8261 phy->flags &= ~FLAGS_SFP_NOT_APPROVED; in bnx2x_verify_sfp_module()
8291 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); in bnx2x_verify_sfp_module()
8299 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_verify_sfp_module()
8308 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_verify_sfp_module()
8323 phy->flags |= FLAGS_SFP_NOT_APPROVED; in bnx2x_verify_sfp_module()
8327 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, in bnx2x_wait_for_sfp_module_initialized() argument
8340 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in bnx2x_wait_for_sfp_module_initialized()
8342 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, in bnx2x_wait_for_sfp_module_initialized()
8345 rc = bnx2x_read_sfp_module_eeprom(phy, params, in bnx2x_wait_for_sfp_module_initialized()
8356 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0, in bnx2x_wait_for_sfp_module_initialized()
8362 struct bnx2x_phy *phy, in bnx2x_8727_power_module() argument
8377 if (phy->flags & FLAGS_NOC) in bnx2x_8727_power_module()
8387 bnx2x_cl45_write(bp, phy, in bnx2x_8727_power_module()
8394 struct bnx2x_phy *phy, in bnx2x_8726_set_limiting_mode() argument
8399 bnx2x_cl45_read(bp, phy, in bnx2x_8726_set_limiting_mode()
8408 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8422 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8426 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8430 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8434 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8443 struct bnx2x_phy *phy, in bnx2x_8727_set_limiting_mode() argument
8448 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_limiting_mode()
8453 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8458 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_limiting_mode()
8463 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8468 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8476 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, in bnx2x_8727_specific_func() argument
8484 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_8727_specific_func()
8487 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) in bnx2x_8727_specific_func()
8488 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_8727_specific_func()
8491 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8494 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8497 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8500 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_specific_func()
8504 if (phy->flags & FLAGS_NOC) in bnx2x_8727_specific_func()
8509 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_specific_func()
8511 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8584 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, in bnx2x_warpcore_hw_reset() argument
8599 struct bnx2x_phy *phy, in bnx2x_power_sfp_module() argument
8605 switch (phy->type) { in bnx2x_power_sfp_module()
8608 bnx2x_8727_power_module(params->bp, phy, power); in bnx2x_power_sfp_module()
8618 struct bnx2x_phy *phy, in bnx2x_warpcore_set_limiting_mode() argument
8625 u8 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_set_limiting_mode()
8627 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8645 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8648 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8652 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_set_limiting_mode()
8653 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_set_limiting_mode()
8658 struct bnx2x_phy *phy, in bnx2x_set_limiting_mode() argument
8661 switch (phy->type) { in bnx2x_set_limiting_mode()
8663 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8667 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8670 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); in bnx2x_set_limiting_mode()
8675 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, in bnx2x_sfp_module_detection() argument
8686 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_sfp_module_detection()
8690 bnx2x_power_sfp_module(params, phy, 1); in bnx2x_sfp_module_detection()
8691 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { in bnx2x_sfp_module_detection()
8694 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { in bnx2x_sfp_module_detection()
8706 bnx2x_power_sfp_module(params, phy, 0); in bnx2x_sfp_module_detection()
8717 bnx2x_set_limiting_mode(params, phy, edc_mode); in bnx2x_sfp_module_detection()
8725 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_sfp_module_detection()
8733 struct bnx2x_phy *phy; in bnx2x_handle_module_detect_int() local
8737 phy = ¶ms->phy[INT_PHY]; in bnx2x_handle_module_detect_int()
8739 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_handle_module_detect_int()
8741 phy = ¶ms->phy[EXT_PHY1]; in bnx2x_handle_module_detect_int()
8759 bnx2x_set_aer_mmd(params, phy); in bnx2x_handle_module_detect_int()
8761 bnx2x_power_sfp_module(params, phy, 1); in bnx2x_handle_module_detect_int()
8765 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { in bnx2x_handle_module_detect_int()
8766 bnx2x_sfp_module_detection(phy, params); in bnx2x_handle_module_detect_int()
8773 bnx2x_cl45_read(bp, phy, in bnx2x_handle_module_detect_int()
8780 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_handle_module_detect_int()
8781 bnx2x_warpcore_config_sfi(phy, params); in bnx2x_handle_module_detect_int()
8782 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_handle_module_detect_int()
8795 phy->media_type = ETH_PHY_NOT_PRESENT; in bnx2x_handle_module_detect_int()
8803 struct bnx2x_phy *phy, in bnx2x_sfp_mask_fault() argument
8808 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_mask_fault()
8811 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_mask_fault()
8815 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); in bnx2x_sfp_mask_fault()
8820 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); in bnx2x_sfp_mask_fault()
8825 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, in bnx2x_8706_8726_read_status() argument
8834 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8837 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, in bnx2x_8706_8726_read_status()
8841 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8843 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8847 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8849 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8851 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8853 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8867 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_8706_8726_read_status()
8873 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8706_8726_read_status()
8875 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8706_8726_read_status()
8887 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, in bnx2x_8706_config_init() argument
8899 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8706_config_init()
8900 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8706_config_init()
8904 bnx2x_cl45_read(bp, phy, in bnx2x_8706_config_init()
8919 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); in bnx2x_8706_config_init()
8923 val |= (phy->rx_preemphasis[i] & 0x7); in bnx2x_8706_config_init()
8926 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); in bnx2x_8706_config_init()
8930 if (phy->req_line_speed == SPEED_10000) { in bnx2x_8706_config_init()
8933 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8936 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8940 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8947 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8951 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8954 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8957 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8961 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8963 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8966 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8970 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8706_config_init()
8983 bnx2x_cl45_read(bp, phy, in bnx2x_8706_config_init()
8986 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8993 static int bnx2x_8706_read_status(struct bnx2x_phy *phy, in bnx2x_8706_read_status() argument
8997 return bnx2x_8706_8726_read_status(phy, params, vars); in bnx2x_8706_read_status()
9003 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, in bnx2x_8726_config_loopback() argument
9008 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); in bnx2x_8726_config_loopback()
9011 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, in bnx2x_8726_external_rom_boot() argument
9019 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9023 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9028 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9032 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9041 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9046 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8726_external_rom_boot()
9049 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, in bnx2x_8726_read_status() argument
9055 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); in bnx2x_8726_read_status()
9057 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_status()
9070 static int bnx2x_8726_config_init(struct bnx2x_phy *phy, in bnx2x_8726_config_init() argument
9077 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in bnx2x_8726_config_init()
9078 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8726_config_init()
9080 bnx2x_8726_external_rom_boot(phy, params); in bnx2x_8726_config_init()
9087 bnx2x_sfp_module_detection(phy, params); in bnx2x_8726_config_init()
9089 if (phy->req_line_speed == SPEED_1000) { in bnx2x_8726_config_init()
9091 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9093 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9095 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9097 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9100 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_8726_config_init()
9101 (phy->speed_cap_mask & in bnx2x_8726_config_init()
9103 ((phy->speed_cap_mask & in bnx2x_8726_config_init()
9108 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_8726_config_init()
9109 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9111 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9113 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9115 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9117 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9122 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9124 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9129 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9138 phy->tx_preemphasis[0], in bnx2x_8726_config_init()
9139 phy->tx_preemphasis[1]); in bnx2x_8726_config_init()
9140 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9143 phy->tx_preemphasis[0]); in bnx2x_8726_config_init()
9145 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9148 phy->tx_preemphasis[1]); in bnx2x_8726_config_init()
9155 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, in bnx2x_8726_link_reset() argument
9161 bnx2x_cl45_write(bp, phy, in bnx2x_8726_link_reset()
9170 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, in bnx2x_8727_set_link_led() argument
9178 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_set_link_led()
9195 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_link_led()
9201 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_link_led()
9205 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_link_led()
9211 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_link_led()
9216 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, in bnx2x_8727_hw_reset() argument
9231 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, in bnx2x_8727_config_speed() argument
9237 if ((phy->req_line_speed == SPEED_1000) || in bnx2x_8727_config_speed()
9238 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { in bnx2x_8727_config_speed()
9240 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9242 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9244 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_speed()
9251 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_speed()
9255 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9259 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_8727_config_speed()
9260 ((phy->speed_cap_mask & in bnx2x_8727_config_speed()
9262 ((phy->speed_cap_mask & in bnx2x_8727_config_speed()
9267 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9269 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9275 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9278 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9280 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9282 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9288 static int bnx2x_8727_config_init(struct bnx2x_phy *phy, in bnx2x_8727_config_init() argument
9297 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8727_config_init()
9301 bnx2x_8727_specific_func(phy, params, PHY_INIT); in bnx2x_8727_config_init()
9305 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9312 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_config_init()
9314 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9318 bnx2x_set_disable_pmd_transmit(params, phy, 0); in bnx2x_8727_config_init()
9320 bnx2x_8727_power_module(bp, phy, 1); in bnx2x_8727_config_init()
9322 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9325 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9328 bnx2x_8727_config_speed(phy, params); in bnx2x_8727_config_init()
9335 phy->tx_preemphasis[0], in bnx2x_8727_config_init()
9336 phy->tx_preemphasis[1]); in bnx2x_8727_config_init()
9337 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9339 phy->tx_preemphasis[0]); in bnx2x_8727_config_init()
9341 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9343 phy->tx_preemphasis[1]); in bnx2x_8727_config_init()
9357 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9361 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9363 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9366 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9374 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, in bnx2x_8727_handle_mod_abs() argument
9383 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9391 phy->media_type = ETH_PHY_NOT_PRESENT; in bnx2x_8727_handle_mod_abs()
9400 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_handle_mod_abs()
9402 bnx2x_cl45_write(bp, phy, in bnx2x_8727_handle_mod_abs()
9409 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9425 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_handle_mod_abs()
9427 bnx2x_cl45_write(bp, phy, in bnx2x_8727_handle_mod_abs()
9436 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9443 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_8727_handle_mod_abs()
9445 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) in bnx2x_8727_handle_mod_abs()
9446 bnx2x_sfp_module_detection(phy, params); in bnx2x_8727_handle_mod_abs()
9451 bnx2x_8727_config_speed(phy, params); in bnx2x_8727_handle_mod_abs()
9459 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, in bnx2x_8727_read_status() argument
9470 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9477 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9483 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, in bnx2x_8727_read_status()
9486 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9492 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9498 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { in bnx2x_8727_read_status()
9500 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9519 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9523 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9528 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9532 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9535 bnx2x_8727_power_module(params->bp, phy, 0); in bnx2x_8727_read_status()
9542 bnx2x_8727_handle_mod_abs(phy, params); in bnx2x_8727_read_status()
9544 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9549 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { in bnx2x_8727_read_status()
9551 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_8727_read_status()
9557 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9582 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_read_status()
9585 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_read_status()
9594 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_8727_read_status()
9600 (phy->req_line_speed == SPEED_1000)) { in bnx2x_8727_read_status()
9601 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9611 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9618 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, in bnx2x_8727_link_reset() argument
9624 bnx2x_set_disable_pmd_transmit(params, phy, 1); in bnx2x_8727_link_reset()
9627 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_8727_link_reset()
9629 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); in bnx2x_8727_link_reset()
9636 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, in bnx2x_save_848xx_spirom_version() argument
9650 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_save_848xx_spirom_version()
9651 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { in bnx2x_save_848xx_spirom_version()
9652 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9654 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9659 bnx2x_cl45_write(bp, phy, reg_set[i].devad, in bnx2x_save_848xx_spirom_version()
9663 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9672 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9678 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); in bnx2x_save_848xx_spirom_version()
9679 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); in bnx2x_save_848xx_spirom_version()
9680 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); in bnx2x_save_848xx_spirom_version()
9682 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9691 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9696 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9698 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); in bnx2x_save_848xx_spirom_version()
9701 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9706 struct bnx2x_phy *phy) in bnx2x_848xx_set_led() argument
9719 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_led()
9725 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_led()
9730 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_848xx_set_led()
9733 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_848xx_set_led()
9734 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) in bnx2x_848xx_set_led()
9740 bnx2x_cl45_read_or_write(bp, phy, in bnx2x_848xx_set_led()
9745 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, in bnx2x_848xx_specific_func() argument
9752 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && in bnx2x_848xx_specific_func()
9753 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { in bnx2x_848xx_specific_func()
9755 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848xx_specific_func()
9764 bnx2x_848xx_set_led(bp, phy); in bnx2x_848xx_specific_func()
9769 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, in bnx2x_848xx_cmn_config_init() argument
9776 bnx2x_848xx_specific_func(phy, params, PHY_INIT); in bnx2x_848xx_cmn_config_init()
9777 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9781 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9785 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_848xx_cmn_config_init()
9786 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9790 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9797 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_848xx_cmn_config_init()
9798 (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9800 (phy->req_line_speed == SPEED_1000)) { in bnx2x_848xx_cmn_config_init()
9803 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_848xx_cmn_config_init()
9809 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9814 if (phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_848xx_cmn_config_init()
9815 if (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9824 if (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9833 if ((phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9835 (phy->supported & SUPPORTED_10baseT_Full)) { in bnx2x_848xx_cmn_config_init()
9841 if ((phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9843 (phy->supported & SUPPORTED_10baseT_Half)) { in bnx2x_848xx_cmn_config_init()
9851 if ((phy->req_line_speed == SPEED_100) && in bnx2x_848xx_cmn_config_init()
9852 (phy->supported & in bnx2x_848xx_cmn_config_init()
9857 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9864 if ((phy->req_line_speed == SPEED_10) && in bnx2x_848xx_cmn_config_init()
9865 (phy->supported & in bnx2x_848xx_cmn_config_init()
9869 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9875 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9879 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_848xx_cmn_config_init()
9885 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && in bnx2x_848xx_cmn_config_init()
9886 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || in bnx2x_848xx_cmn_config_init()
9888 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9892 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_848xx_cmn_config_init()
9893 (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9895 (phy->req_line_speed == SPEED_10000)) { in bnx2x_848xx_cmn_config_init()
9900 bp, phy, in bnx2x_848xx_cmn_config_init()
9904 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9908 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9916 static int bnx2x_8481_config_init(struct bnx2x_phy *phy, in bnx2x_8481_config_init() argument
9927 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8481_config_init()
9929 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in bnx2x_8481_config_init()
9930 return bnx2x_848xx_cmn_config_init(phy, params, vars); in bnx2x_8481_config_init()
9935 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, in bnx2x_84833_cmd_hdlr() argument
9943 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9947 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9960 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9964 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9967 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9981 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9985 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9991 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, in bnx2x_84833_pair_swap_cfg() argument
10012 status = bnx2x_84833_cmd_hdlr(phy, params, in bnx2x_84833_pair_swap_cfg()
10058 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, in bnx2x_84833_hw_reset_phy() argument
10070 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_84833_hw_reset_phy()
10073 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_84833_hw_reset_phy()
10091 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, in bnx2x_8483x_disable_eee() argument
10102 rc = bnx2x_84833_cmd_hdlr(phy, params, in bnx2x_8483x_disable_eee()
10109 return bnx2x_eee_disable(phy, params, vars); in bnx2x_8483x_disable_eee()
10112 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, in bnx2x_8483x_enable_eee() argument
10120 rc = bnx2x_84833_cmd_hdlr(phy, params, in bnx2x_8483x_enable_eee()
10127 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); in bnx2x_8483x_enable_eee()
10131 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, in bnx2x_848x3_config_init() argument
10149 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in bnx2x_848x3_config_init()
10155 bnx2x_cl45_write(bp, phy, in bnx2x_848x3_config_init()
10160 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_848x3_config_init()
10164 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && in bnx2x_848x3_config_init()
10165 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { in bnx2x_848x3_config_init()
10172 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); in bnx2x_848x3_config_init()
10173 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); in bnx2x_848x3_config_init()
10177 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10213 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) in bnx2x_848x3_config_init()
10216 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10221 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_848x3_config_init()
10222 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { in bnx2x_848x3_config_init()
10223 bnx2x_84833_pair_swap_cfg(phy, params, vars); in bnx2x_848x3_config_init()
10230 rc = bnx2x_84833_cmd_hdlr(phy, params, in bnx2x_848x3_config_init()
10237 rc = bnx2x_848xx_cmn_config_init(phy, params, vars); in bnx2x_848x3_config_init()
10239 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848x3_config_init()
10241 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in bnx2x_848x3_config_init()
10247 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10253 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10257 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10267 bnx2x_8483x_disable_eee(phy, params, vars); in bnx2x_848x3_config_init()
10271 if ((phy->req_duplex == DUPLEX_FULL) && in bnx2x_848x3_config_init()
10275 rc = bnx2x_8483x_enable_eee(phy, params, vars); in bnx2x_848x3_config_init()
10277 rc = bnx2x_8483x_disable_eee(phy, params, vars); in bnx2x_848x3_config_init()
10286 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_848x3_config_init()
10287 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { in bnx2x_848x3_config_init()
10289 bnx2x_cl45_read_and_write(bp, phy, in bnx2x_848x3_config_init()
10297 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, in bnx2x_848xx_read_status() argument
10308 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10310 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10320 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_848xx_read_status()
10325 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_read_status()
10330 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10361 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10368 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10380 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_848xx_read_status()
10383 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10401 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10411 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10419 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_848xx_read_status()
10420 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) in bnx2x_848xx_read_status()
10421 bnx2x_eee_an_resolve(phy, params, vars); in bnx2x_848xx_read_status()
10436 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, in bnx2x_8481_hw_reset() argument
10445 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, in bnx2x_8481_link_reset() argument
10448 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10450 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10454 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, in bnx2x_848x3_link_reset() argument
10466 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in bnx2x_848x3_link_reset()
10471 bnx2x_cl45_read(bp, phy, in bnx2x_848x3_link_reset()
10475 bnx2x_cl45_write(bp, phy, in bnx2x_848x3_link_reset()
10481 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, in bnx2x_848xx_set_link_led() argument
10502 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10507 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10512 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10517 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10523 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10538 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10543 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10548 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10553 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10559 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10563 if (phy->type == in bnx2x_848xx_set_link_led()
10580 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10594 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10601 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10607 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10612 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10617 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10622 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10627 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10631 if (phy->type == in bnx2x_848xx_set_link_led()
10648 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10664 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10673 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10680 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10685 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10690 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10695 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10709 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10715 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10721 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10725 if (phy->type == in bnx2x_848xx_set_link_led()
10730 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10749 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_848xx_set_link_led()
10757 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, in bnx2x_54618se_specific_func() argument
10767 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10770 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_specific_func()
10775 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10779 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10786 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, in bnx2x_54618se_config_init() argument
10816 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10818 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_54618se_config_init()
10824 bnx2x_54618se_specific_func(phy, params, PHY_INIT); in bnx2x_54618se_config_init()
10826 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10829 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10833 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10839 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_54618se_config_init()
10850 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10854 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10858 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10867 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_54618se_config_init()
10868 (phy->speed_cap_mask & in bnx2x_54618se_config_init()
10870 (phy->req_line_speed == SPEED_1000)) { in bnx2x_54618se_config_init()
10873 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_54618se_config_init()
10879 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10882 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10887 if (phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_54618se_config_init()
10888 if (phy->speed_cap_mask & in bnx2x_54618se_config_init()
10894 if (phy->speed_cap_mask & in bnx2x_54618se_config_init()
10900 if (phy->speed_cap_mask & in bnx2x_54618se_config_init()
10906 if (phy->speed_cap_mask & in bnx2x_54618se_config_init()
10915 if (phy->req_line_speed == SPEED_100) { in bnx2x_54618se_config_init()
10918 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10923 if (phy->req_line_speed == SPEED_10) { in bnx2x_54618se_config_init()
10925 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10931 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { in bnx2x_54618se_config_init()
10934 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, in bnx2x_54618se_config_init()
10937 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); in bnx2x_54618se_config_init()
10939 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); in bnx2x_54618se_config_init()
10944 bnx2x_eee_disable(phy, params, vars); in bnx2x_54618se_config_init()
10946 (phy->req_duplex == DUPLEX_FULL) && in bnx2x_54618se_config_init()
10954 bnx2x_eee_advertise(phy, params, vars, in bnx2x_54618se_config_init()
10958 bnx2x_eee_disable(phy, params, vars); in bnx2x_54618se_config_init()
10964 if (phy->flags & FLAGS_EEE) { in bnx2x_54618se_config_init()
10974 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_54618se_config_init()
10979 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10983 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_54618se_config_init()
10986 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10993 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, in bnx2x_5461x_set_link_led() argument
10999 bnx2x_cl22_write(bp, phy, in bnx2x_5461x_set_link_led()
11002 bnx2x_cl22_read(bp, phy, in bnx2x_5461x_set_link_led()
11022 bnx2x_cl22_write(bp, phy, in bnx2x_5461x_set_link_led()
11029 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, in bnx2x_54618se_link_reset() argument
11039 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); in bnx2x_54618se_link_reset()
11054 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, in bnx2x_54618se_read_status() argument
11064 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11070 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11107 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11113 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11123 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_54618se_read_status()
11127 bnx2x_cl22_read(bp, phy, 0x5, &val); in bnx2x_54618se_read_status()
11145 bnx2x_cl22_read(bp, phy, 0xa, &val); in bnx2x_54618se_read_status()
11153 if ((phy->flags & FLAGS_EEE) && in bnx2x_54618se_read_status()
11155 bnx2x_eee_an_resolve(phy, params, vars); in bnx2x_54618se_read_status()
11161 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, in bnx2x_54618se_config_loopback() argument
11172 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); in bnx2x_54618se_config_loopback()
11179 bnx2x_cl22_read(bp, phy, 0x00, &val); in bnx2x_54618se_config_loopback()
11182 bnx2x_cl22_write(bp, phy, 0x00, val); in bnx2x_54618se_config_loopback()
11188 bnx2x_cl22_write(bp, phy, 0x18, 7); in bnx2x_54618se_config_loopback()
11189 bnx2x_cl22_read(bp, phy, 0x18, &val); in bnx2x_54618se_config_loopback()
11190 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); in bnx2x_54618se_config_loopback()
11204 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, in bnx2x_7101_config_loopback() argument
11209 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_loopback()
11213 static int bnx2x_7101_config_init(struct bnx2x_phy *phy, in bnx2x_7101_config_init() argument
11226 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_7101_config_init()
11228 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11231 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11234 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_7101_config_init()
11236 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11239 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11243 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11246 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11249 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); in bnx2x_7101_config_init()
11253 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, in bnx2x_7101_read_status() argument
11260 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11262 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11266 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11268 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11275 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11282 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_7101_read_status()
11283 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_7101_read_status()
11306 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_sfx7101_sp_sw_reset() argument
11310 bnx2x_cl45_read(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11317 bnx2x_cl45_write(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11322 bnx2x_cl45_read(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11331 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, in bnx2x_7101_hw_reset() argument
11341 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, in bnx2x_7101_set_link_led() argument
11358 bnx2x_cl45_write(bp, phy, in bnx2x_7101_set_link_led()
11864 struct bnx2x_phy *phy, u8 port, in bnx2x_populate_preemphasis() argument
11892 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); in bnx2x_populate_preemphasis()
11893 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); in bnx2x_populate_preemphasis()
11895 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); in bnx2x_populate_preemphasis()
11896 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); in bnx2x_populate_preemphasis()
11923 struct bnx2x_phy *phy) in bnx2x_populate_int_phy() argument
11939 *phy = phy_warpcore; in bnx2x_populate_int_phy()
11941 phy->flags |= FLAGS_4_PORT_MODE; in bnx2x_populate_int_phy()
11943 phy->flags &= ~FLAGS_4_PORT_MODE; in bnx2x_populate_int_phy()
11954 phy->supported &= (SUPPORTED_10baseT_Half | in bnx2x_populate_int_phy()
11963 phy->media_type = ETH_PHY_BASE_T; in bnx2x_populate_int_phy()
11966 phy->supported &= (SUPPORTED_1000baseT_Full | in bnx2x_populate_int_phy()
11971 phy->media_type = ETH_PHY_XFP_FIBER; in bnx2x_populate_int_phy()
11974 phy->supported &= (SUPPORTED_1000baseT_Full | in bnx2x_populate_int_phy()
11979 phy->media_type = ETH_PHY_SFPP_10G_FIBER; in bnx2x_populate_int_phy()
11982 phy->media_type = ETH_PHY_KR; in bnx2x_populate_int_phy()
11983 phy->supported &= (SUPPORTED_1000baseT_Full | in bnx2x_populate_int_phy()
11991 phy->media_type = ETH_PHY_KR; in bnx2x_populate_int_phy()
11992 phy->flags |= FLAGS_WC_DUAL_MODE; in bnx2x_populate_int_phy()
11993 phy->supported &= (SUPPORTED_20000baseMLD2_Full | in bnx2x_populate_int_phy()
11999 phy->media_type = ETH_PHY_KR; in bnx2x_populate_int_phy()
12000 phy->flags |= FLAGS_WC_DUAL_MODE; in bnx2x_populate_int_phy()
12001 phy->supported &= (SUPPORTED_20000baseKR2_Full | in bnx2x_populate_int_phy()
12008 phy->flags &= ~FLAGS_TX_ERROR_CHECK; in bnx2x_populate_int_phy()
12021 phy->flags |= FLAGS_MDC_MDIO_WA; in bnx2x_populate_int_phy()
12023 phy->flags |= FLAGS_MDC_MDIO_WA_B0; in bnx2x_populate_int_phy()
12030 *phy = phy_serdes; in bnx2x_populate_int_phy()
12036 *phy = phy_xgxs; in bnx2x_populate_int_phy()
12043 phy->addr = (u8)phy_addr; in bnx2x_populate_int_phy()
12044 phy->mdio_ctrl = bnx2x_get_emac_base(bp, in bnx2x_populate_int_phy()
12048 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; in bnx2x_populate_int_phy()
12050 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; in bnx2x_populate_int_phy()
12053 port, phy->addr, phy->mdio_ctrl); in bnx2x_populate_int_phy()
12055 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); in bnx2x_populate_int_phy()
12064 struct bnx2x_phy *phy) in bnx2x_populate_ext_phy() argument
12075 *phy = phy_8073; in bnx2x_populate_ext_phy()
12078 *phy = phy_8705; in bnx2x_populate_ext_phy()
12081 *phy = phy_8706; in bnx2x_populate_ext_phy()
12085 *phy = phy_8726; in bnx2x_populate_ext_phy()
12090 *phy = phy_8727; in bnx2x_populate_ext_phy()
12091 phy->flags |= FLAGS_NOC; in bnx2x_populate_ext_phy()
12096 *phy = phy_8727; in bnx2x_populate_ext_phy()
12099 *phy = phy_8481; in bnx2x_populate_ext_phy()
12102 *phy = phy_84823; in bnx2x_populate_ext_phy()
12105 *phy = phy_84833; in bnx2x_populate_ext_phy()
12108 *phy = phy_84834; in bnx2x_populate_ext_phy()
12112 *phy = phy_54618se; in bnx2x_populate_ext_phy()
12114 phy->flags |= FLAGS_EEE; in bnx2x_populate_ext_phy()
12117 *phy = phy_7101; in bnx2x_populate_ext_phy()
12120 *phy = phy_null; in bnx2x_populate_ext_phy()
12123 *phy = phy_null; in bnx2x_populate_ext_phy()
12131 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); in bnx2x_populate_ext_phy()
12132 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); in bnx2x_populate_ext_phy()
12141 phy->ver_addr = shmem_base + offsetof(struct shmem_region, in bnx2x_populate_ext_phy()
12153 phy->ver_addr = shmem2_base + in bnx2x_populate_ext_phy()
12164 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); in bnx2x_populate_ext_phy()
12166 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_populate_ext_phy()
12167 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && in bnx2x_populate_ext_phy()
12168 (phy->ver_addr)) { in bnx2x_populate_ext_phy()
12172 u32 raw_ver = REG_RD(bp, phy->ver_addr); in bnx2x_populate_ext_phy()
12175 phy->supported &= ~(SUPPORTED_100baseT_Half | in bnx2x_populate_ext_phy()
12182 phy->addr, phy->mdio_ctrl); in bnx2x_populate_ext_phy()
12187 u32 shmem2_base, u8 port, struct bnx2x_phy *phy) in bnx2x_populate_phy() argument
12190 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; in bnx2x_populate_phy()
12192 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); in bnx2x_populate_phy()
12194 port, phy); in bnx2x_populate_phy()
12199 struct bnx2x_phy *phy, in bnx2x_phy_def_cfg() argument
12209 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12217 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12224 phy_index, link_config, phy->speed_cap_mask); in bnx2x_phy_def_cfg()
12226 phy->req_duplex = DUPLEX_FULL; in bnx2x_phy_def_cfg()
12229 phy->req_duplex = DUPLEX_HALF; in bnx2x_phy_def_cfg()
12231 phy->req_line_speed = SPEED_10; in bnx2x_phy_def_cfg()
12234 phy->req_duplex = DUPLEX_HALF; in bnx2x_phy_def_cfg()
12236 phy->req_line_speed = SPEED_100; in bnx2x_phy_def_cfg()
12239 phy->req_line_speed = SPEED_1000; in bnx2x_phy_def_cfg()
12242 phy->req_line_speed = SPEED_2500; in bnx2x_phy_def_cfg()
12245 phy->req_line_speed = SPEED_10000; in bnx2x_phy_def_cfg()
12248 phy->req_line_speed = SPEED_AUTO_NEG; in bnx2x_phy_def_cfg()
12254 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; in bnx2x_phy_def_cfg()
12257 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; in bnx2x_phy_def_cfg()
12260 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; in bnx2x_phy_def_cfg()
12263 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; in bnx2x_phy_def_cfg()
12266 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_phy_def_cfg()
12308 struct bnx2x_phy *phy; in bnx2x_phy_probe() local
12326 phy = ¶ms->phy[actual_phy_idx]; in bnx2x_phy_probe()
12329 phy) != 0) { in bnx2x_phy_probe()
12336 *phy = phy_null; in bnx2x_phy_probe()
12339 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) in bnx2x_phy_probe()
12344 phy->flags &= ~FLAGS_TX_ERROR_CHECK; in bnx2x_phy_probe()
12348 phy->flags |= FLAGS_MDC_MDIO_WA_G; in bnx2x_phy_probe()
12362 media_types |= ((phy->media_type & in bnx2x_phy_probe()
12369 bnx2x_phy_def_cfg(params, phy, phy_index); in bnx2x_phy_probe()
12432 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); in bnx2x_init_xmac_loopback()
12433 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); in bnx2x_init_xmac_loopback()
12434 params->phy[INT_PHY].config_loopback( in bnx2x_init_xmac_loopback()
12435 ¶ms->phy[INT_PHY], in bnx2x_init_xmac_loopback()
12461 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; in bnx2x_init_xgxs_loopback()
12499 if (params->phy[phy_index].config_loopback) in bnx2x_init_xgxs_loopback()
12500 params->phy[phy_index].config_loopback( in bnx2x_init_xgxs_loopback()
12501 ¶ms->phy[phy_index], in bnx2x_init_xgxs_loopback()
12544 struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; in bnx2x_avoid_link_flap() local
12545 if (phy->phy_specific_func) { in bnx2x_avoid_link_flap()
12547 phy->phy_specific_func(phy, params, PHY_INIT); in bnx2x_avoid_link_flap()
12549 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || in bnx2x_avoid_link_flap()
12550 (phy->media_type == ETH_PHY_SFP_1G_FIBER) || in bnx2x_avoid_link_flap()
12551 (phy->media_type == ETH_PHY_DA_TWINAX)) in bnx2x_avoid_link_flap()
12552 bnx2x_verify_sfp_module(phy, params); in bnx2x_avoid_link_flap()
12800 if (params->phy[phy_index].link_reset) { in bnx2x_link_reset()
12802 ¶ms->phy[phy_index]); in bnx2x_link_reset()
12803 params->phy[phy_index].link_reset( in bnx2x_link_reset()
12804 ¶ms->phy[phy_index], in bnx2x_link_reset()
12807 if (params->phy[phy_index].flags & in bnx2x_link_reset()
12819 if (params->phy[INT_PHY].link_reset) in bnx2x_link_reset()
12820 params->phy[INT_PHY].link_reset( in bnx2x_link_reset()
12821 ¶ms->phy[INT_PHY], params); in bnx2x_link_reset()
12902 struct bnx2x_phy phy[PORT_MAX]; in bnx2x_8073_common_init_phy() local
12928 port_of_path, &phy[port]) != in bnx2x_8073_common_init_phy()
12949 bnx2x_cl45_write(bp, &phy[port], in bnx2x_8073_common_init_phy()
12958 if (phy[PORT_0].addr & 0x1) { in bnx2x_8073_common_init_phy()
12959 phy_blk[PORT_0] = &(phy[PORT_1]); in bnx2x_8073_common_init_phy()
12960 phy_blk[PORT_1] = &(phy[PORT_0]); in bnx2x_8073_common_init_phy()
12962 phy_blk[PORT_0] = &(phy[PORT_0]); in bnx2x_8073_common_init_phy()
12963 phy_blk[PORT_1] = &(phy[PORT_1]); in bnx2x_8073_common_init_phy()
13030 struct bnx2x_phy phy; in bnx2x_8726_common_init_phy() local
13053 port, &phy) != in bnx2x_8726_common_init_phy()
13060 bnx2x_cl45_write(bp, &phy, in bnx2x_8726_common_init_phy()
13125 struct bnx2x_phy phy[PORT_MAX]; in bnx2x_8727_common_init_phy() local
13169 port_of_path, &phy[port]) != in bnx2x_8727_common_init_phy()
13184 bnx2x_cl45_write(bp, &phy[port], in bnx2x_8727_common_init_phy()
13190 if (phy[PORT_0].addr & 0x1) { in bnx2x_8727_common_init_phy()
13191 phy_blk[PORT_0] = &(phy[PORT_1]); in bnx2x_8727_common_init_phy()
13192 phy_blk[PORT_1] = &(phy[PORT_0]); in bnx2x_8727_common_init_phy()
13194 phy_blk[PORT_0] = &(phy[PORT_0]); in bnx2x_8727_common_init_phy()
13195 phy_blk[PORT_1] = &(phy[PORT_1]); in bnx2x_8727_common_init_phy()
13498 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, in bnx2x_sfp_tx_fault_detection() argument
13534 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { in bnx2x_sfp_tx_fault_detection()
13543 struct bnx2x_phy *phy) in bnx2x_kr2_recovery() argument
13547 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); in bnx2x_kr2_recovery()
13548 bnx2x_warpcore_restart_AN_KR(phy, params); in bnx2x_kr2_recovery()
13553 struct bnx2x_phy *phy) in bnx2x_check_kr2_wa() argument
13569 sigdet = bnx2x_warpcore_get_sigdet(phy, params); in bnx2x_check_kr2_wa()
13572 bnx2x_kr2_recovery(params, vars, phy); in bnx2x_check_kr2_wa()
13578 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_check_kr2_wa()
13579 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_check_kr2_wa()
13581 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_check_kr2_wa()
13583 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_check_kr2_wa()
13585 bnx2x_set_aer_mmd(params, phy); in bnx2x_check_kr2_wa()
13590 bnx2x_kr2_recovery(params, vars, phy); in bnx2x_check_kr2_wa()
13609 bnx2x_kr2_recovery(params, vars, phy); in bnx2x_check_kr2_wa()
13617 bnx2x_disable_kr2(params, vars, phy); in bnx2x_check_kr2_wa()
13619 bnx2x_warpcore_restart_AN_KR(phy, params); in bnx2x_check_kr2_wa()
13629 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { in bnx2x_period_func()
13630 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); in bnx2x_period_func()
13639 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; in bnx2x_period_func() local
13640 bnx2x_set_aer_mmd(params, phy); in bnx2x_period_func()
13641 if ((phy->supported & SUPPORTED_20000baseKR2_Full) && in bnx2x_period_func()
13642 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) in bnx2x_period_func()
13643 bnx2x_check_kr2_wa(params, vars, phy); in bnx2x_period_func()
13646 bnx2x_warpcore_config_runtime(phy, params, vars); in bnx2x_period_func()
13653 if (bnx2x_is_sfp_module_plugged(phy, params)) { in bnx2x_period_func()
13654 bnx2x_sfp_tx_fault_detection(phy, params, vars); in bnx2x_period_func()
13673 struct bnx2x_phy phy; in bnx2x_fan_failure_det_req() local
13677 port, &phy) in bnx2x_fan_failure_det_req()
13682 fan_failure_det_req |= (phy.flags & in bnx2x_fan_failure_det_req()
13701 if (params->phy[phy_index].hw_reset) { in bnx2x_hw_reset_phy()
13702 params->phy[phy_index].hw_reset( in bnx2x_hw_reset_phy()
13703 ¶ms->phy[phy_index], in bnx2x_hw_reset_phy()
13705 params->phy[phy_index] = phy_null; in bnx2x_hw_reset_phy()
13725 struct bnx2x_phy phy; in bnx2x_init_mod_abs_int() local
13729 shmem2_base, port, &phy) in bnx2x_init_mod_abs_int()
13734 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { in bnx2x_init_mod_abs_int()