1459 				   params->phy[phy_index].mdio_ctrl);  in bnx2x_set_mdio_emac_per_phy()
2604 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_write()
2605 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in bnx2x_cl22_write()
2612 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl22_write()
2617 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_write()
2627 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in bnx2x_cl22_write()
2640 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_read()
2641 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in bnx2x_cl22_read()
2648 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl22_read()
2653 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_read()
2666 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in bnx2x_cl22_read()
2683 		bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);  in bnx2x_cl45_read()
2687 		bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_read()
2693 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl45_read()
2698 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_read()
2714 		REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl45_read()
2719 			val = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_read()
2743 		bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_read()
2758 		bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);  in bnx2x_cl45_write()
2762 		bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_write()
2769 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl45_write()
2774 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_write()
2789 		REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl45_write()
2794 			tmp = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_write()
2816 		bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_write()
8291 	fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);  in bnx2x_verify_sfp_module()
11375 	.mdio_ctrl	= 0,
11401 	.mdio_ctrl	= 0,
11436 	.mdio_ctrl	= 0,
11471 	.mdio_ctrl	= 0,
11509 	.mdio_ctrl	= 0,
11538 	.mdio_ctrl	= 0,
11569 	.mdio_ctrl	= 0,
11597 	.mdio_ctrl	= 0,
11628 	.mdio_ctrl	= 0,
11660 	.mdio_ctrl	= 0,
11690 	.mdio_ctrl	= 0,
11727 	.mdio_ctrl	= 0,
11764 	.mdio_ctrl	= 0,
11798 	.mdio_ctrl	= 0,
11831 	.mdio_ctrl	= 0,
12044 	phy->mdio_ctrl = bnx2x_get_emac_base(bp,  in bnx2x_populate_int_phy()
12053 		   port, phy->addr, phy->mdio_ctrl);  in bnx2x_populate_int_phy()
12164 	phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);  in bnx2x_populate_ext_phy()
12182 		   phy->addr, phy->mdio_ctrl);  in bnx2x_populate_ext_phy()