1422 			       u32 emac_base)  in bnx2x_set_mdio_clk()  argument
1429 	cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_set_mdio_clk()
1447 	REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);  in bnx2x_set_mdio_clk()
1481 	u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;  in bnx2x_emac_init()  local
1493 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_init()
1498 		val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_init()
1817 	u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;  in bnx2x_emac_enable()  local
1847 	bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,  in bnx2x_emac_enable()
1849 	bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,  in bnx2x_emac_enable()
1853 		bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,  in bnx2x_emac_enable()
1856 		bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,  in bnx2x_emac_enable()
1862 				bnx2x_bits_en(bp, emac_base +  in bnx2x_emac_enable()
1867 				bnx2x_bits_en(bp, emac_base +  in bnx2x_emac_enable()
1872 			bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,  in bnx2x_emac_enable()
1876 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);  in bnx2x_emac_enable()
1905 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_enable()
2564 	u32 emac_base = 0;  in bnx2x_get_emac_base()  local
2570 			emac_base = GRCBASE_EMAC1;  in bnx2x_get_emac_base()
2572 			emac_base = GRCBASE_EMAC0;  in bnx2x_get_emac_base()
2576 			emac_base = GRCBASE_EMAC0;  in bnx2x_get_emac_base()
2578 			emac_base = GRCBASE_EMAC1;  in bnx2x_get_emac_base()
2581 		emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;  in bnx2x_get_emac_base()
2584 		emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;  in bnx2x_get_emac_base()
2589 	return emac_base;  in bnx2x_get_emac_base()
3318 	u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;  in bnx2x_set_serdes_access()  local
3322 	REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);  in bnx2x_set_serdes_access()
3324 	REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);  in bnx2x_set_serdes_access()
6298 	u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;  in bnx2x_set_led()  local