4318 	u32 cfg_pin;  in bnx2x_get_mod_abs_int_cfg()  local
4322 		cfg_pin = (REG_RD(bp, shmem_base +  in bnx2x_get_mod_abs_int_cfg()
4334 		if ((cfg_pin < PIN_CFG_GPIO0_P0) ||  in bnx2x_get_mod_abs_int_cfg()
4335 		    (cfg_pin > PIN_CFG_GPIO3_P1)) {  in bnx2x_get_mod_abs_int_cfg()
4338 			   cfg_pin);  in bnx2x_get_mod_abs_int_cfg()
4342 		*gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;  in bnx2x_get_mod_abs_int_cfg()
4343 		*gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;  in bnx2x_get_mod_abs_int_cfg()
4459 	u32 cfg_pin;  in bnx2x_sfp_e3_set_transmitter()  local
4462 	cfg_pin = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_e3_set_transmitter()
4470 	bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);  in bnx2x_sfp_e3_set_transmitter()
4472 		bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);  in bnx2x_sfp_e3_set_transmitter()
10793 	u32 cfg_pin;  in bnx2x_54618se_config_init()  local
10803 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_54618se_config_init()
10810 	bnx2x_set_cfg_pin(bp, cfg_pin, 1);  in bnx2x_54618se_config_init()
11033 	u32 cfg_pin;  in bnx2x_54618se_link_reset()  local
11044 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_54618se_link_reset()
11051 	bnx2x_set_cfg_pin(bp, cfg_pin, 0);  in bnx2x_54618se_link_reset()
13332 	u32 cfg_pin;  in bnx2x_check_over_curr()  local
13336 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_check_over_curr()
13343 	if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)  in bnx2x_check_over_curr()
13503 	u32 cfg_pin, value = 0;  in bnx2x_sfp_tx_fault_detection()  local
13507 	cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,  in bnx2x_sfp_tx_fault_detection()
13512 	if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {  in bnx2x_sfp_tx_fault_detection()
13513 		DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);  in bnx2x_sfp_tx_fault_detection()