Lines Matching refs:REG_WR
229 REG_WR(bp, reg, val); in bnx2x_bits_en()
238 REG_WR(bp, reg, val); in bnx2x_bits_dis()
266 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
385 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); in bnx2x_get_epio()
407 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); in bnx2x_set_epio()
411 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); in bnx2x_set_epio()
458 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); in bnx2x_ets_e2e3a0_disabled()
467 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_e2e3a0_disabled()
469 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); in bnx2x_ets_e2e3a0_disabled()
473 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_e2e3a0_disabled()
477 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); in bnx2x_ets_e2e3a0_disabled()
478 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); in bnx2x_ets_e2e3a0_disabled()
479 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); in bnx2x_ets_e2e3a0_disabled()
481 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); in bnx2x_ets_e2e3a0_disabled()
482 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); in bnx2x_ets_e2e3a0_disabled()
483 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); in bnx2x_ets_e2e3a0_disabled()
485 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_e2e3a0_disabled()
489 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
490 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
492 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
493 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
495 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_e2e3a0_disabled()
543 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
551 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
553 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
557 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
559 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
561 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
585 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); in bnx2x_ets_e3b0_nig_disabled()
586 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
588 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); in bnx2x_ets_e3b0_nig_disabled()
589 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); in bnx2x_ets_e3b0_nig_disabled()
594 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : in bnx2x_ets_e3b0_nig_disabled()
601 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); in bnx2x_ets_e3b0_nig_disabled()
602 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
605 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, in bnx2x_ets_e3b0_nig_disabled()
607 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); in bnx2x_ets_e3b0_nig_disabled()
618 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); in bnx2x_ets_e3b0_nig_disabled()
620 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); in bnx2x_ets_e3b0_nig_disabled()
622 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in bnx2x_ets_e3b0_nig_disabled()
631 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : in bnx2x_ets_e3b0_nig_disabled()
633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : in bnx2x_ets_e3b0_nig_disabled()
635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : in bnx2x_ets_e3b0_nig_disabled()
637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : in bnx2x_ets_e3b0_nig_disabled()
639 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : in bnx2x_ets_e3b0_nig_disabled()
641 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : in bnx2x_ets_e3b0_nig_disabled()
644 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); in bnx2x_ets_e3b0_nig_disabled()
645 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); in bnx2x_ets_e3b0_nig_disabled()
646 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); in bnx2x_ets_e3b0_nig_disabled()
679 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
705 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); in bnx2x_ets_e3b0_pbf_disabled()
708 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
713 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); in bnx2x_ets_e3b0_pbf_disabled()
716 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
718 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : in bnx2x_ets_e3b0_pbf_disabled()
722 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in bnx2x_ets_e3b0_pbf_disabled()
725 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in bnx2x_ets_e3b0_pbf_disabled()
739 REG_WR(bp, base_weight + (0x4 * i), 0); in bnx2x_ets_e3b0_pbf_disabled()
806 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : in bnx2x_ets_e3b0_cli_map()
809 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in bnx2x_ets_e3b0_cli_map()
812 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in bnx2x_ets_e3b0_cli_map()
816 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in bnx2x_ets_e3b0_cli_map()
889 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); in bnx2x_ets_e3b0_set_cos_bw()
891 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); in bnx2x_ets_e3b0_set_cos_bw()
1113 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1116 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1122 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1124 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1127 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1247 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); in bnx2x_ets_bw_limit_common()
1254 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); in bnx2x_ets_bw_limit_common()
1256 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, in bnx2x_ets_bw_limit_common()
1258 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, in bnx2x_ets_bw_limit_common()
1262 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); in bnx2x_ets_bw_limit_common()
1265 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_bw_limit_common()
1273 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_bw_limit_common()
1276 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, in bnx2x_ets_bw_limit_common()
1278 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, in bnx2x_ets_bw_limit_common()
1307 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); in bnx2x_ets_bw_limit()
1308 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); in bnx2x_ets_bw_limit()
1310 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); in bnx2x_ets_bw_limit()
1311 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); in bnx2x_ets_bw_limit()
1328 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); in bnx2x_ets_strict()
1332 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1334 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_strict()
1336 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1339 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); in bnx2x_ets_strict()
1349 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); in bnx2x_ets_strict()
1392 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in bnx2x_update_pfc_xmac()
1393 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in bnx2x_update_pfc_xmac()
1394 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in bnx2x_update_pfc_xmac()
1400 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in bnx2x_update_pfc_xmac()
1401 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in bnx2x_update_pfc_xmac()
1402 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in bnx2x_update_pfc_xmac()
1406 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, in bnx2x_update_pfc_xmac()
1411 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, in bnx2x_update_pfc_xmac()
1447 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); in bnx2x_set_mdio_clk()
1485 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_emac_init()
1488 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_emac_init()
1526 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, in bnx2x_set_xumac_nig()
1528 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, in bnx2x_set_xumac_nig()
1530 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : in bnx2x_set_xumac_nig()
1550 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_set_umac_rxtx()
1560 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_umac_enable()
1564 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_umac_enable()
1570 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_umac_enable()
1603 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1609 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, in bnx2x_umac_enable()
1611 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); in bnx2x_umac_enable()
1613 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); in bnx2x_umac_enable()
1617 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, in bnx2x_umac_enable()
1622 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, in bnx2x_umac_enable()
1630 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1639 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1644 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_umac_enable()
1675 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_xmac_init()
1679 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_xmac_init()
1685 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); in bnx2x_xmac_init()
1688 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); in bnx2x_xmac_init()
1691 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); in bnx2x_xmac_init()
1696 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); in bnx2x_xmac_init()
1701 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); in bnx2x_xmac_init()
1705 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_xmac_init()
1709 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_xmac_init()
1728 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, in bnx2x_set_xmac_rxtx()
1730 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, in bnx2x_set_xmac_rxtx()
1738 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); in bnx2x_set_xmac_rxtx()
1760 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); in bnx2x_xmac_enable()
1766 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, in bnx2x_xmac_enable()
1769 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_xmac_enable()
1770 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_xmac_enable()
1775 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); in bnx2x_xmac_enable()
1778 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); in bnx2x_xmac_enable()
1785 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); in bnx2x_xmac_enable()
1786 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); in bnx2x_xmac_enable()
1788 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); in bnx2x_xmac_enable()
1803 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); in bnx2x_xmac_enable()
1823 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_emac_enable()
1827 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); in bnx2x_emac_enable()
1837 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); in bnx2x_emac_enable()
1839 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bnx2x_emac_enable()
1844 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); in bnx2x_emac_enable()
1913 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); in bnx2x_emac_enable()
1921 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); in bnx2x_emac_enable()
1924 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); in bnx2x_emac_enable()
1925 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1926 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1929 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); in bnx2x_emac_enable()
1936 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); in bnx2x_emac_enable()
1937 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); in bnx2x_emac_enable()
1939 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
2103 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); in bnx2x_pfc_nig_rx_priority_mask()
2111 REG_WR(bp, params->shmem_base + in bnx2x_update_mng()
2121 REG_WR(bp, params->shmem2_base + in bnx2x_update_link_attr()
2175 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : in bnx2x_update_pfc_nig()
2177 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : in bnx2x_update_pfc_nig()
2179 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : in bnx2x_update_pfc_nig()
2181 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : in bnx2x_update_pfc_nig()
2184 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : in bnx2x_update_pfc_nig()
2187 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : in bnx2x_update_pfc_nig()
2190 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : in bnx2x_update_pfc_nig()
2194 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : in bnx2x_update_pfc_nig()
2198 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : in bnx2x_update_pfc_nig()
2209 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : in bnx2x_update_pfc_nig()
2213 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : in bnx2x_update_pfc_nig()
2217 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : in bnx2x_update_pfc_nig()
2271 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); in bnx2x_update_pfc()
2415 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_bmac_enable()
2420 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_bmac_enable()
2424 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2431 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); in bnx2x_bmac_enable()
2432 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); in bnx2x_bmac_enable()
2433 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); in bnx2x_bmac_enable()
2439 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); in bnx2x_bmac_enable()
2440 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2441 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); in bnx2x_bmac_enable()
2442 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2443 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); in bnx2x_bmac_enable()
2444 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2485 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); in bnx2x_pbf_update()
2509 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); in bnx2x_pbf_update()
2511 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); in bnx2x_pbf_update()
2518 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_pbf_update()
2520 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); in bnx2x_pbf_update()
2532 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); in bnx2x_pbf_update()
2537 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); in bnx2x_pbf_update()
2539 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); in bnx2x_pbf_update()
2542 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); in bnx2x_pbf_update()
2605 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_write()
2612 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl22_write()
2627 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_write()
2641 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_read()
2648 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl22_read()
2666 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_read()
2693 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2714 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2769 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2789 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2916 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), in bnx2x_eee_set_timers()
2966 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); in bnx2x_eee_disable()
2983 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); in bnx2x_eee_advertise()
3007 REG_WR(bp, params->shmem2_base + in bnx2x_update_mng_eee()
3111 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3115 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); in bnx2x_bsc_read()
3122 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3146 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3321 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); in bnx2x_set_serdes_access()
3322 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); in bnx2x_set_serdes_access()
3324 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); in bnx2x_set_serdes_access()
3327 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); in bnx2x_set_serdes_access()
3339 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in bnx2x_serdes_deassert()
3341 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in bnx2x_serdes_deassert()
3345 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, in bnx2x_serdes_deassert()
3357 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); in bnx2x_xgxs_specific_func()
3358 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, in bnx2x_xgxs_specific_func()
3375 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in bnx2x_xgxs_deassert()
3377 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in bnx2x_xgxs_deassert()
6103 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, in bnx2x_rearm_latch_signal()
6251 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6272 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6314 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); in bnx2x_set_led()
6315 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6345 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6346 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); in bnx2x_set_led()
6366 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); in bnx2x_set_led()
6371 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6373 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6378 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6392 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6396 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); in bnx2x_set_led()
6399 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in bnx2x_set_led()
6402 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in bnx2x_set_led()
6404 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + in bnx2x_set_led()
6416 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 in bnx2x_set_led()
6418 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + in bnx2x_set_led()
6420 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + in bnx2x_set_led()
6601 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, in bnx2x_int_link_reset()
6642 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in bnx2x_update_link_down()
6646 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_update_link_down()
6656 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), in bnx2x_update_link_down()
6658 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), in bnx2x_update_link_down()
6707 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + in bnx2x_update_link_up()
6709 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); in bnx2x_update_link_up()
6710 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + in bnx2x_update_link_up()
6746 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); in bnx2x_update_link_up()
6777 REG_WR(bp, addr, val); in bnx2x_chng_link_count()
6839 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_update()
6980 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, in bnx2x_link_update()
7067 REG_WR(bp, ver_addr, spirom_ver); in bnx2x_save_spirom_version()
8229 REG_WR(bp, sync_offset, media_types); in bnx2x_get_edc_mode()
8590 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); in bnx2x_warpcore_hw_reset()
8593 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); in bnx2x_warpcore_hw_reset()
8594 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); in bnx2x_warpcore_hw_reset()
8595 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); in bnx2x_warpcore_hw_reset()
11193 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_54618se_config_loopback()
11198 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_54618se_config_loopback()
12367 REG_WR(bp, sync_offset, media_types); in bnx2x_phy_probe()
12394 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_bmac_loopback()
12413 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_emac_loopback()
12439 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xmac_loopback()
12454 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_umac_loopback()
12504 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xgxs_loopback()
12517 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); in bnx2x_set_rx_filter()
12520 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, in bnx2x_set_rx_filter()
12524 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_set_rx_filter()
12563 REG_WR(bp, GRCBASE_MISC + in bnx2x_avoid_link_flap()
12567 REG_WR(bp, GRCBASE_MISC + in bnx2x_avoid_link_flap()
12591 REG_WR(bp, params->lfa_base + in bnx2x_avoid_link_flap()
12595 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_avoid_link_flap()
12614 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12618 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12622 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12627 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12638 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12657 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12771 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in bnx2x_link_reset()
12775 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
12776 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
12787 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_reset()
12826 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_link_reset()
12828 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
12829 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
12835 REG_WR(bp, xmac_base + XMAC_REG_CTRL, in bnx2x_link_reset()
12855 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_lfa_reset()
12890 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_lfa_reset()
13036 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); in bnx2x_8726_common_init_phy()
13301 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); in bnx2x_common_init_phy()
13404 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_analyze_link_error()
13417 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_analyze_link_error()
13466 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_check_half_open_conn()
13467 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_check_half_open_conn()
13758 REG_WR(bp, sync_offset, vars->aeu_int_mask); in bnx2x_init_mod_abs_int()
13771 REG_WR(bp, offset, aeu_mask); in bnx2x_init_mod_abs_int()
13776 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); in bnx2x_init_mod_abs_int()