116 	unsigned int reg_val;  in amd8111e_read_phy()  local
119 	reg_val = readl(mmio + PHY_ACCESS);  in amd8111e_read_phy()
120 	while (reg_val & PHY_CMD_ACTIVE)  in amd8111e_read_phy()
121 		reg_val = readl( mmio + PHY_ACCESS );  in amd8111e_read_phy()
126 		reg_val = readl(mmio + PHY_ACCESS);  in amd8111e_read_phy()
128 	} while (--repeat && (reg_val & PHY_CMD_ACTIVE));  in amd8111e_read_phy()
129 	if(reg_val & PHY_RD_ERR)  in amd8111e_read_phy()
132 	*val = reg_val & 0xffff;  in amd8111e_read_phy()
146 	unsigned int reg_val;  in amd8111e_write_phy()  local
148 	reg_val = readl(mmio + PHY_ACCESS);  in amd8111e_write_phy()
149 	while (reg_val & PHY_CMD_ACTIVE)  in amd8111e_write_phy()
150 		reg_val = readl( mmio + PHY_ACCESS );  in amd8111e_write_phy()
156 		reg_val = readl(mmio + PHY_ACCESS);  in amd8111e_write_phy()
158 	} while (--repeat && (reg_val & PHY_CMD_ACTIVE));  in amd8111e_write_phy()
160 	if(reg_val & PHY_RD_ERR)  in amd8111e_write_phy()
174 	unsigned int reg_val;  in amd8111e_mdio_read()  local
176 	amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);  in amd8111e_mdio_read()
177 	return reg_val;  in amd8111e_mdio_read()
435 	int i,reg_val;  in amd8111e_restart()  local
450 	reg_val = readl(mmio + CTRL1);  in amd8111e_restart()
451 	reg_val &= ~XMTSP_MASK;  in amd8111e_restart()
452 	writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );  in amd8111e_restart()
510 	unsigned int reg_val;  in amd8111e_init_hw_default()  local
547 	reg_val = readl(mmio + INT0);  in amd8111e_init_hw_default()
548 	writel(reg_val, mmio + INT0);  in amd8111e_init_hw_default()
581 	reg_val = readl(mmio + SRAM_SIZE);  in amd8111e_init_hw_default()