66 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev)  in mei_me_mecbrw_read()  argument
68 	return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);  in mei_me_mecbrw_read()
77 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data)  in mei_me_hcbww_write()  argument
79 	mei_me_reg_write(to_me_hw(dev), H_CB_WW, data);  in mei_me_hcbww_write()
89 static inline u32 mei_me_mecsr_read(const struct mei_device *dev)  in mei_me_mecsr_read()  argument
93 	reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA);  in mei_me_mecsr_read()
94 	trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg);  in mei_me_mecsr_read()
106 static inline u32 mei_hcsr_read(const struct mei_device *dev)  in mei_hcsr_read()  argument
110 	reg = mei_me_reg_read(to_me_hw(dev), H_CSR);  in mei_hcsr_read()
111 	trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg);  in mei_hcsr_read()
122 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg)  in mei_hcsr_write()  argument
124 	trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg);  in mei_hcsr_write()
125 	mei_me_reg_write(to_me_hw(dev), H_CSR, reg);  in mei_hcsr_write()
135 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg)  in mei_hcsr_set()  argument
138 	mei_hcsr_write(dev, reg);  in mei_hcsr_set()
149 static int mei_me_fw_status(struct mei_device *dev,  in mei_me_fw_status()  argument
152 	struct pci_dev *pdev = to_pci_dev(dev->dev);  in mei_me_fw_status()
153 	struct mei_me_hw *hw = to_me_hw(dev);  in mei_me_fw_status()
177 static void mei_me_hw_config(struct mei_device *dev)  in mei_me_hw_config()  argument
179 	struct mei_me_hw *hw = to_me_hw(dev);  in mei_me_hw_config()
180 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_hw_config()
182 	dev->hbuf_depth = (hcsr & H_CBD) >> 24;  in mei_me_hw_config()
195 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)  in mei_me_pg_state()  argument
197 	struct mei_me_hw *hw = to_me_hw(dev);  in mei_me_pg_state()
207 static void mei_me_intr_clear(struct mei_device *dev)  in mei_me_intr_clear()  argument
209 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_intr_clear()
212 		mei_hcsr_write(dev, hcsr);  in mei_me_intr_clear()
219 static void mei_me_intr_enable(struct mei_device *dev)  in mei_me_intr_enable()  argument
221 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_intr_enable()
224 	mei_hcsr_set(dev, hcsr);  in mei_me_intr_enable()
232 static void mei_me_intr_disable(struct mei_device *dev)  in mei_me_intr_disable()  argument
234 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_intr_disable()
237 	mei_hcsr_set(dev, hcsr);  in mei_me_intr_disable()
245 static void mei_me_hw_reset_release(struct mei_device *dev)  in mei_me_hw_reset_release()  argument
247 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset_release()
251 	mei_hcsr_set(dev, hcsr);  in mei_me_hw_reset_release()
264 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)  in mei_me_hw_reset()  argument
266 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset()
274 		dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);  in mei_me_hw_reset()
276 		mei_hcsr_set(dev, hcsr);  in mei_me_hw_reset()
277 		hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset()
287 	dev->recvd_hw_ready = false;  in mei_me_hw_reset()
288 	mei_hcsr_write(dev, hcsr);  in mei_me_hw_reset()
294 	hcsr = mei_hcsr_read(dev);  in mei_me_hw_reset()
297 		dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);  in mei_me_hw_reset()
300 		dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);  in mei_me_hw_reset()
303 		mei_me_hw_reset_release(dev);  in mei_me_hw_reset()
313 static void mei_me_host_set_ready(struct mei_device *dev)  in mei_me_host_set_ready()  argument
315 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_host_set_ready()
318 	mei_hcsr_set(dev, hcsr);  in mei_me_host_set_ready()
327 static bool mei_me_host_is_ready(struct mei_device *dev)  in mei_me_host_is_ready()  argument
329 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_host_is_ready()
340 static bool mei_me_hw_is_ready(struct mei_device *dev)  in mei_me_hw_is_ready()  argument
342 	u32 mecsr = mei_me_mecsr_read(dev);  in mei_me_hw_is_ready()
354 static int mei_me_hw_ready_wait(struct mei_device *dev)  in mei_me_hw_ready_wait()  argument
356 	mutex_unlock(&dev->device_lock);  in mei_me_hw_ready_wait()
357 	wait_event_timeout(dev->wait_hw_ready,  in mei_me_hw_ready_wait()
358 			dev->recvd_hw_ready,  in mei_me_hw_ready_wait()
360 	mutex_lock(&dev->device_lock);  in mei_me_hw_ready_wait()
361 	if (!dev->recvd_hw_ready) {  in mei_me_hw_ready_wait()
362 		dev_err(dev->dev, "wait hw ready failed\n");  in mei_me_hw_ready_wait()
366 	mei_me_hw_reset_release(dev);  in mei_me_hw_ready_wait()
367 	dev->recvd_hw_ready = false;  in mei_me_hw_ready_wait()
377 static int mei_me_hw_start(struct mei_device *dev)  in mei_me_hw_start()  argument
379 	int ret = mei_me_hw_ready_wait(dev);  in mei_me_hw_start()
383 	dev_dbg(dev->dev, "hw is ready\n");  in mei_me_hw_start()
385 	mei_me_host_set_ready(dev);  in mei_me_hw_start()
397 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)  in mei_hbuf_filled_slots()  argument
402 	hcsr = mei_hcsr_read(dev);  in mei_hbuf_filled_slots()
417 static bool mei_me_hbuf_is_empty(struct mei_device *dev)  in mei_me_hbuf_is_empty()  argument
419 	return mei_hbuf_filled_slots(dev) == 0;  in mei_me_hbuf_is_empty()
429 static int mei_me_hbuf_empty_slots(struct mei_device *dev)  in mei_me_hbuf_empty_slots()  argument
433 	filled_slots = mei_hbuf_filled_slots(dev);  in mei_me_hbuf_empty_slots()
434 	empty_slots = dev->hbuf_depth - filled_slots;  in mei_me_hbuf_empty_slots()
437 	if (filled_slots > dev->hbuf_depth)  in mei_me_hbuf_empty_slots()
450 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)  in mei_me_hbuf_max_len()  argument
452 	return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);  in mei_me_hbuf_max_len()
465 static int mei_me_write_message(struct mei_device *dev,  in mei_me_write_message()  argument
477 	dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));  in mei_me_write_message()
479 	empty_slots = mei_hbuf_empty_slots(dev);  in mei_me_write_message()
480 	dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots);  in mei_me_write_message()
486 	mei_me_hcbww_write(dev, *((u32 *) header));  in mei_me_write_message()
489 		mei_me_hcbww_write(dev, reg_buf[i]);  in mei_me_write_message()
496 		mei_me_hcbww_write(dev, reg);  in mei_me_write_message()
499 	hcsr = mei_hcsr_read(dev) | H_IG;  in mei_me_write_message()
500 	mei_hcsr_set(dev, hcsr);  in mei_me_write_message()
501 	if (!mei_me_hw_is_ready(dev))  in mei_me_write_message()
514 static int mei_me_count_full_read_slots(struct mei_device *dev)  in mei_me_count_full_read_slots()  argument
520 	me_csr = mei_me_mecsr_read(dev);  in mei_me_count_full_read_slots()
530 	dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots);  in mei_me_count_full_read_slots()
543 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,  in mei_me_read_slots()  argument
550 		*reg_buf++ = mei_me_mecbrw_read(dev);  in mei_me_read_slots()
553 		u32 reg = mei_me_mecbrw_read(dev);  in mei_me_read_slots()
558 	hcsr = mei_hcsr_read(dev) | H_IG;  in mei_me_read_slots()
559 	mei_hcsr_set(dev, hcsr);  in mei_me_read_slots()
568 static void mei_me_pg_set(struct mei_device *dev)  in mei_me_pg_set()  argument
570 	struct mei_me_hw *hw = to_me_hw(dev);  in mei_me_pg_set()
574 	trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);  in mei_me_pg_set()
578 	trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);  in mei_me_pg_set()
587 static void mei_me_pg_unset(struct mei_device *dev)  in mei_me_pg_unset()  argument
589 	struct mei_me_hw *hw = to_me_hw(dev);  in mei_me_pg_unset()
593 	trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);  in mei_me_pg_unset()
599 	trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);  in mei_me_pg_unset()
610 int mei_me_pg_enter_sync(struct mei_device *dev)  in mei_me_pg_enter_sync()  argument
612 	struct mei_me_hw *hw = to_me_hw(dev);  in mei_me_pg_enter_sync()
616 	dev->pg_event = MEI_PG_EVENT_WAIT;  in mei_me_pg_enter_sync()
618 	ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);  in mei_me_pg_enter_sync()
622 	mutex_unlock(&dev->device_lock);  in mei_me_pg_enter_sync()
623 	wait_event_timeout(dev->wait_pg,  in mei_me_pg_enter_sync()
624 		dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);  in mei_me_pg_enter_sync()
625 	mutex_lock(&dev->device_lock);  in mei_me_pg_enter_sync()
627 	if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {  in mei_me_pg_enter_sync()
628 		mei_me_pg_set(dev);  in mei_me_pg_enter_sync()
634 	dev->pg_event = MEI_PG_EVENT_IDLE;  in mei_me_pg_enter_sync()
647 int mei_me_pg_exit_sync(struct mei_device *dev)  in mei_me_pg_exit_sync()  argument
649 	struct mei_me_hw *hw = to_me_hw(dev);  in mei_me_pg_exit_sync()
653 	if (dev->pg_event == MEI_PG_EVENT_RECEIVED)  in mei_me_pg_exit_sync()
656 	dev->pg_event = MEI_PG_EVENT_WAIT;  in mei_me_pg_exit_sync()
658 	mei_me_pg_unset(dev);  in mei_me_pg_exit_sync()
660 	mutex_unlock(&dev->device_lock);  in mei_me_pg_exit_sync()
661 	wait_event_timeout(dev->wait_pg,  in mei_me_pg_exit_sync()
662 		dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);  in mei_me_pg_exit_sync()
663 	mutex_lock(&dev->device_lock);  in mei_me_pg_exit_sync()
666 	if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {  in mei_me_pg_exit_sync()
671 	dev->pg_event = MEI_PG_EVENT_INTR_WAIT;  in mei_me_pg_exit_sync()
672 	ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);  in mei_me_pg_exit_sync()
676 	mutex_unlock(&dev->device_lock);  in mei_me_pg_exit_sync()
677 	wait_event_timeout(dev->wait_pg,  in mei_me_pg_exit_sync()
678 		dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);  in mei_me_pg_exit_sync()
679 	mutex_lock(&dev->device_lock);  in mei_me_pg_exit_sync()
681 	if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)  in mei_me_pg_exit_sync()
687 	dev->pg_event = MEI_PG_EVENT_IDLE;  in mei_me_pg_exit_sync()
700 static bool mei_me_pg_in_transition(struct mei_device *dev)  in mei_me_pg_in_transition()  argument
702 	return dev->pg_event >= MEI_PG_EVENT_WAIT &&  in mei_me_pg_in_transition()
703 	       dev->pg_event <= MEI_PG_EVENT_INTR_WAIT;  in mei_me_pg_in_transition()
713 static bool mei_me_pg_is_enabled(struct mei_device *dev)  in mei_me_pg_is_enabled()  argument
715 	u32 reg = mei_me_mecsr_read(dev);  in mei_me_pg_is_enabled()
720 	if (!dev->hbm_f_pg_supported)  in mei_me_pg_is_enabled()
726 	dev_dbg(dev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n",  in mei_me_pg_is_enabled()
728 		dev->version.major_version,  in mei_me_pg_is_enabled()
729 		dev->version.minor_version,  in mei_me_pg_is_enabled()
741 static void mei_me_pg_intr(struct mei_device *dev)  in mei_me_pg_intr()  argument
743 	struct mei_me_hw *hw = to_me_hw(dev);  in mei_me_pg_intr()
745 	if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT)  in mei_me_pg_intr()
748 	dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;  in mei_me_pg_intr()
750 	if (waitqueue_active(&dev->wait_pg))  in mei_me_pg_intr()
751 		wake_up(&dev->wait_pg);  in mei_me_pg_intr()
765 	struct mei_device *dev = (struct mei_device *) dev_id;  in mei_me_irq_quick_handler()  local
766 	u32 hcsr = mei_hcsr_read(dev);  in mei_me_irq_quick_handler()
772 	mei_hcsr_write(dev, hcsr);  in mei_me_irq_quick_handler()
789 	struct mei_device *dev = (struct mei_device *) dev_id;  in mei_me_irq_thread_handler()  local
794 	dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n");  in mei_me_irq_thread_handler()
796 	mutex_lock(&dev->device_lock);  in mei_me_irq_thread_handler()
801 	if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))  in mei_me_irq_thread_handler()
802 		mei_clear_interrupts(dev);  in mei_me_irq_thread_handler()
805 	if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {  in mei_me_irq_thread_handler()
806 		dev_warn(dev->dev, "FW not ready: resetting.\n");  in mei_me_irq_thread_handler()
807 		schedule_work(&dev->reset_work);  in mei_me_irq_thread_handler()
811 	mei_me_pg_intr(dev);  in mei_me_irq_thread_handler()
814 	if (!mei_host_is_ready(dev)) {  in mei_me_irq_thread_handler()
815 		if (mei_hw_is_ready(dev)) {  in mei_me_irq_thread_handler()
816 			dev_dbg(dev->dev, "we need to start the dev.\n");  in mei_me_irq_thread_handler()
817 			dev->recvd_hw_ready = true;  in mei_me_irq_thread_handler()
818 			wake_up(&dev->wait_hw_ready);  in mei_me_irq_thread_handler()
820 			dev_dbg(dev->dev, "Spurious Interrupt\n");  in mei_me_irq_thread_handler()
825 	slots = mei_count_full_read_slots(dev);  in mei_me_irq_thread_handler()
827 		dev_dbg(dev->dev, "slots to read = %08x\n", slots);  in mei_me_irq_thread_handler()
828 		rets = mei_irq_read_handler(dev, &complete_list, &slots);  in mei_me_irq_thread_handler()
836 		if (rets && dev->dev_state != MEI_DEV_RESETTING) {  in mei_me_irq_thread_handler()
837 			dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n",  in mei_me_irq_thread_handler()
839 			schedule_work(&dev->reset_work);  in mei_me_irq_thread_handler()
844 	dev->hbuf_is_ready = mei_hbuf_is_ready(dev);  in mei_me_irq_thread_handler()
851 	if (dev->pg_event != MEI_PG_EVENT_WAIT &&  in mei_me_irq_thread_handler()
852 	    dev->pg_event != MEI_PG_EVENT_RECEIVED) {  in mei_me_irq_thread_handler()
853 		rets = mei_irq_write_handler(dev, &complete_list);  in mei_me_irq_thread_handler()
854 		dev->hbuf_is_ready = mei_hbuf_is_ready(dev);  in mei_me_irq_thread_handler()
857 	mei_irq_compl_handler(dev, &complete_list);  in mei_me_irq_thread_handler()
860 	dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);  in mei_me_irq_thread_handler()
861 	mutex_unlock(&dev->device_lock);  in mei_me_irq_thread_handler()
985 	struct mei_device *dev;  in mei_me_dev_init()  local
988 	dev = kzalloc(sizeof(struct mei_device) +  in mei_me_dev_init()
990 	if (!dev)  in mei_me_dev_init()
992 	hw = to_me_hw(dev);  in mei_me_dev_init()
994 	mei_device_init(dev, &pdev->dev, &mei_me_hw_ops);  in mei_me_dev_init()
996 	return dev;  in mei_me_dev_init()