30 	struct nvkm_xtensa *xtensa = (void *)object;  in _nvkm_xtensa_rd32()  local
31 	return nv_rd32(xtensa, xtensa->addr + addr);  in _nvkm_xtensa_rd32()
37 	struct nvkm_xtensa *xtensa = (void *)object;  in _nvkm_xtensa_wr32()  local
38 	nv_wr32(xtensa, xtensa->addr + addr, data);  in _nvkm_xtensa_wr32()
58 	struct nvkm_xtensa *xtensa = (void *)subdev;  in _nvkm_xtensa_intr()  local
59 	u32 unk104 = nv_ro32(xtensa, 0xd04);  in _nvkm_xtensa_intr()
60 	u32 intr = nv_ro32(xtensa, 0xc20);  in _nvkm_xtensa_intr()
61 	u32 chan = nv_ro32(xtensa, 0xc28);  in _nvkm_xtensa_intr()
62 	u32 unk10c = nv_ro32(xtensa, 0xd0c);  in _nvkm_xtensa_intr()
65 		nv_warn(xtensa, "Watchdog interrupt, engine hung.\n");  in _nvkm_xtensa_intr()
66 	nv_wo32(xtensa, 0xc20, intr);  in _nvkm_xtensa_intr()
67 	intr = nv_ro32(xtensa, 0xc20);  in _nvkm_xtensa_intr()
69 		nv_debug(xtensa, "Enabling FIFO_CTRL\n");  in _nvkm_xtensa_intr()
70 		nv_mask(xtensa, xtensa->addr + 0xd94, 0, xtensa->fifo_val);  in _nvkm_xtensa_intr()
80 	struct nvkm_xtensa *xtensa;  in nvkm_xtensa_create_()  local
85 	xtensa = *pobject;  in nvkm_xtensa_create_()
89 	nv_subdev(xtensa)->intr = _nvkm_xtensa_intr;  in nvkm_xtensa_create_()
90 	xtensa->addr = addr;  in nvkm_xtensa_create_()
98 	struct nvkm_xtensa *xtensa = (void *)object;  in _nvkm_xtensa_init()  local
104 	ret = nvkm_engine_init(&xtensa->base);  in _nvkm_xtensa_init()
108 	if (!xtensa->gpu_fw) {  in _nvkm_xtensa_init()
110 			 xtensa->addr >> 12);  in _nvkm_xtensa_init()
114 			nv_warn(xtensa, "unable to load firmware %s\n", name);  in _nvkm_xtensa_init()
119 			nv_warn(xtensa, "firmware %s too large\n", name);  in _nvkm_xtensa_init()
125 				      &xtensa->gpu_fw);  in _nvkm_xtensa_init()
131 		nv_debug(xtensa, "Loading firmware to address: 0x%llx\n",  in _nvkm_xtensa_init()
132 			 xtensa->gpu_fw->addr);  in _nvkm_xtensa_init()
135 			nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i));  in _nvkm_xtensa_init()
139 	nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */  in _nvkm_xtensa_init()
140 	nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */  in _nvkm_xtensa_init()
142 	nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */  in _nvkm_xtensa_init()
143 	nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */  in _nvkm_xtensa_init()
144 	nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */  in _nvkm_xtensa_init()
146 	nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */  in _nvkm_xtensa_init()
147 	nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */  in _nvkm_xtensa_init()
148 	nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */  in _nvkm_xtensa_init()
150 	tmp = nv_rd32(xtensa, 0x0);  in _nvkm_xtensa_init()
151 	nv_wo32(xtensa, 0xde0, tmp); /* SCRATCH_H2X */  in _nvkm_xtensa_init()
153 	nv_wo32(xtensa, 0xce8, 0xf); /* XT_REGION_SETUP */  in _nvkm_xtensa_init()
155 	nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */  in _nvkm_xtensa_init()
156 	nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */  in _nvkm_xtensa_init()
163 	struct nvkm_xtensa *xtensa = (void *)object;  in _nvkm_xtensa_fini()  local
165 	nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */  in _nvkm_xtensa_fini()
166 	nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */  in _nvkm_xtensa_fini()
169 		nvkm_gpuobj_ref(NULL, &xtensa->gpu_fw);  in _nvkm_xtensa_fini()
171 	return nvkm_engine_fini(&xtensa->base, suspend);  in _nvkm_xtensa_fini()