121 nv40_gr_vs_count(struct nvkm_device *device)  in nv40_gr_vs_count()  argument
124 	switch (device->chipset) {  in nv40_gr_vs_count()
162 	struct nvkm_device *device = ctx->device;  in nv40_gr_construct_general()  local
189 	if (device->chipset == 0x40) {  in nv40_gr_construct_general()
210 		if (nv44_gr_class(ctx->device)) {  in nv40_gr_construct_general()
219 		if (!nv44_gr_class(ctx->device)) {  in nv40_gr_construct_general()
225 		if (device->chipset == 0x4c ||  in nv40_gr_construct_general()
226 		    (device->chipset & 0xf0) == 0x60)  in nv40_gr_construct_general()
233 	switch (device->chipset) {  in nv40_gr_construct_general()
242 		switch (device->chipset) {  in nv40_gr_construct_general()
268 	struct nvkm_device *device = ctx->device;  in nv40_gr_construct_state3d()  local
271 	if (device->chipset == 0x40) {  in nv40_gr_construct_state3d()
275 	if (device->chipset == 0x46 || device->chipset == 0x47 ||  in nv40_gr_construct_state3d()
276 	    device->chipset == 0x49 || device->chipset == 0x4b) {  in nv40_gr_construct_state3d()
280 		if (device->chipset == 0x46)  in nv40_gr_construct_state3d()
291 	if (device->chipset == 0x40) {  in nv40_gr_construct_state3d()
299 	switch (device->chipset) {  in nv40_gr_construct_state3d()
318 	if (device->chipset == 0x40) {  in nv40_gr_construct_state3d()
329 	cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1);  in nv40_gr_construct_state3d()
331 	cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5);  in nv40_gr_construct_state3d()
332 	gr_def(ctx, 0x401b28, device->chipset == 0x40 ?  in nv40_gr_construct_state3d()
343 	if (device->chipset != 0x44 && device->chipset != 0x4a &&  in nv40_gr_construct_state3d()
344 	    device->chipset != 0x4e)  in nv40_gr_construct_state3d()
373 	struct nvkm_device *device = ctx->device;  in nv40_gr_construct_state3d_2()  local
377 	cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2);  in nv40_gr_construct_state3d_2()
378 	switch (device->chipset) {  in nv40_gr_construct_state3d_2()
395 	if (device->chipset != 0x40)  in nv40_gr_construct_state3d_2()
397 	switch (device->chipset) {  in nv40_gr_construct_state3d_2()
410 	cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9);  in nv40_gr_construct_state3d_2()
413 	switch (device->chipset) {  in nv40_gr_construct_state3d_2()
430 	gr_def(ctx, 0x40249c, device->chipset <= 0x43 ?  in nv40_gr_construct_state3d_2()
434 	if (device->chipset == 0x40)  in nv40_gr_construct_state3d_2()
439 	switch (device->chipset) {  in nv40_gr_construct_state3d_2()
447 		if (device->chipset != 0x47) { /* belong at end!! */  in nv40_gr_construct_state3d_2()
472 	gr_def(ctx, 0x402c00, device->chipset == 0x40 ?  in nv40_gr_construct_state3d_2()
474 	switch (device->chipset) {  in nv40_gr_construct_state3d_2()
487 		if (device->chipset == 0x40)  in nv40_gr_construct_state3d_2()
490 		if (device->chipset <= 0x42)  in nv40_gr_construct_state3d_2()
493 		if (device->chipset <= 0x4a)  in nv40_gr_construct_state3d_2()
497 		cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13);  in nv40_gr_construct_state3d_2()
499 		if (device->chipset != 0x40)  in nv40_gr_construct_state3d_2()
504 	cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3);  in nv40_gr_construct_state3d_2()
505 	cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3);  in nv40_gr_construct_state3d_2()
506 	cp_ctx(ctx, 0x403420, nv40_gr_vs_count(ctx->device));  in nv40_gr_construct_state3d_2()
507 	for (i = 0; i < nv40_gr_vs_count(ctx->device); i++)  in nv40_gr_construct_state3d_2()
510 	if (device->chipset != 0x40) {  in nv40_gr_construct_state3d_2()
518 	switch (device->chipset) {  in nv40_gr_construct_state3d_2()
529 	if (device->chipset != 0x4e)  in nv40_gr_construct_state3d_2()
537 	int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684;  in nv40_gr_construct_state3d_3()
552 	struct nvkm_device *device = ctx->device;  in nv40_gr_construct_shader()  local
557 	vs_nr    = nv40_gr_vs_count(ctx->device);  in nv40_gr_construct_shader()
559 	vs_nr_b1 = device->chipset == 0x40 ? 128 : 64;  in nv40_gr_construct_shader()
560 	if (device->chipset == 0x40) {  in nv40_gr_construct_shader()
565 	if (device->chipset == 0x41 || device->chipset == 0x42) {  in nv40_gr_construct_shader()
572 		vs_len = nv44_gr_class(device) ? 0x4980/4 : 0x4a40/4;  in nv40_gr_construct_shader()
576 	cp_out(ctx, nv44_gr_class(device) ? 0x800029 : 0x800041);  in nv40_gr_construct_shader()
662 nv40_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem)  in nv40_grctx_fill()  argument
665 			     .device = device,  in nv40_grctx_fill()
672 nv40_grctx_init(struct nvkm_device *device, u32 *size)  in nv40_grctx_init()  argument
676 		.device = device,  in nv40_grctx_init()
687 	nv_wr32(device, 0x400324, 0);  in nv40_grctx_init()
689 		nv_wr32(device, 0x400328, ctxprog[i]);  in nv40_grctx_init()