Lines Matching refs:ppgtt
1195 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); in gen8_emit_bb_start() local
1203 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); in gen8_emit_bb_start()
1731 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; in populate_lr_context() local
1736 if (!ppgtt) in populate_lr_context()
1737 ppgtt = dev_priv->mm.aliasing_ppgtt; in populate_lr_context()
1818 reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[3]->daddr); in populate_lr_context()
1819 reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[3]->daddr); in populate_lr_context()
1820 reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[2]->daddr); in populate_lr_context()
1821 reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[2]->daddr); in populate_lr_context()
1822 reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[1]->daddr); in populate_lr_context()
1823 reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[1]->daddr); in populate_lr_context()
1824 reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[0]->daddr); in populate_lr_context()
1825 reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[0]->daddr); in populate_lr_context()