442 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,  in gen8_write_pdp()  argument
449 	ret = intel_ring_begin(ring, 6);  in gen8_write_pdp()
453 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));  in gen8_write_pdp()
454 	intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));  in gen8_write_pdp()
455 	intel_ring_emit(ring, (u32)(val >> 32));  in gen8_write_pdp()
456 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));  in gen8_write_pdp()
457 	intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));  in gen8_write_pdp()
458 	intel_ring_emit(ring, (u32)(val));  in gen8_write_pdp()
459 	intel_ring_advance(ring);  in gen8_write_pdp()
465 			  struct intel_engine_cs *ring)  in gen8_mm_switch()  argument
474 		ret = gen8_write_pdp(ring, i, addr);  in gen8_mm_switch()
956 			 struct intel_engine_cs *ring)  in hsw_mm_switch()  argument
961 	ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);  in hsw_mm_switch()
965 	ret = intel_ring_begin(ring, 6);  in hsw_mm_switch()
969 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));  in hsw_mm_switch()
970 	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));  in hsw_mm_switch()
971 	intel_ring_emit(ring, PP_DIR_DCLV_2G);  in hsw_mm_switch()
972 	intel_ring_emit(ring, RING_PP_DIR_BASE(ring));  in hsw_mm_switch()
973 	intel_ring_emit(ring, get_pd_offset(ppgtt));  in hsw_mm_switch()
974 	intel_ring_emit(ring, MI_NOOP);  in hsw_mm_switch()
975 	intel_ring_advance(ring);  in hsw_mm_switch()
981 			  struct intel_engine_cs *ring)  in vgpu_mm_switch()  argument
985 	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);  in vgpu_mm_switch()
986 	I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));  in vgpu_mm_switch()
991 			  struct intel_engine_cs *ring)  in gen7_mm_switch()  argument
996 	ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);  in gen7_mm_switch()
1000 	ret = intel_ring_begin(ring, 6);  in gen7_mm_switch()
1004 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));  in gen7_mm_switch()
1005 	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));  in gen7_mm_switch()
1006 	intel_ring_emit(ring, PP_DIR_DCLV_2G);  in gen7_mm_switch()
1007 	intel_ring_emit(ring, RING_PP_DIR_BASE(ring));  in gen7_mm_switch()
1008 	intel_ring_emit(ring, get_pd_offset(ppgtt));  in gen7_mm_switch()
1009 	intel_ring_emit(ring, MI_NOOP);  in gen7_mm_switch()
1010 	intel_ring_advance(ring);  in gen7_mm_switch()
1013 	if (ring->id != RCS) {  in gen7_mm_switch()
1014 		ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);  in gen7_mm_switch()
1023 			  struct intel_engine_cs *ring)  in gen6_mm_switch()  argument
1029 	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);  in gen6_mm_switch()
1030 	I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));  in gen6_mm_switch()
1032 	POSTING_READ(RING_PP_DIR_DCLV(ring));  in gen6_mm_switch()
1040 	struct intel_engine_cs *ring;  in gen8_ppgtt_enable()  local
1043 	for_each_ring(ring, dev_priv, j) {  in gen8_ppgtt_enable()
1044 		I915_WRITE(RING_MODE_GEN7(ring),  in gen8_ppgtt_enable()
1052 	struct intel_engine_cs *ring;  in gen7_ppgtt_enable()  local
1068 	for_each_ring(ring, dev_priv, i) {  in gen7_ppgtt_enable()
1070 		I915_WRITE(RING_MODE_GEN7(ring),  in gen7_ppgtt_enable()
1465 	struct intel_engine_cs *ring;  in i915_ppgtt_init_hw()  local
1488 		for_each_ring(ring, dev_priv, i) {  in i915_ppgtt_init_hw()
1489 			ret = ppgtt->switch_mm(ppgtt, ring);  in i915_ppgtt_init_hw()
1600 	struct intel_engine_cs *ring;  in i915_check_and_clear_faults()  local
1606 	for_each_ring(ring, dev_priv, i) {  in i915_check_and_clear_faults()
1608 		fault_reg = I915_READ(RING_FAULT_REG(ring));  in i915_check_and_clear_faults()
1619 			I915_WRITE(RING_FAULT_REG(ring),  in i915_check_and_clear_faults()
1623 	POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));  in i915_check_and_clear_faults()