383 	u32 pp;  in cdv_intel_edp_panel_vdd_on()  local
391 	pp = REG_READ(PP_CONTROL);  in cdv_intel_edp_panel_vdd_on()
393 	pp |= EDP_FORCE_VDD;  in cdv_intel_edp_panel_vdd_on()
394 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_panel_vdd_on()
402 	u32 pp;  in cdv_intel_edp_panel_vdd_off()  local
405 	pp = REG_READ(PP_CONTROL);  in cdv_intel_edp_panel_vdd_off()
407 	pp &= ~EDP_FORCE_VDD;  in cdv_intel_edp_panel_vdd_off()
408 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_panel_vdd_off()
418 	u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE;  in cdv_intel_edp_panel_on()  local
424 	pp = REG_READ(PP_CONTROL);  in cdv_intel_edp_panel_on()
425 	pp &= ~PANEL_UNLOCK_MASK;  in cdv_intel_edp_panel_on()
427 	pp |= (PANEL_UNLOCK_REGS | POWER_TARGET_ON);  in cdv_intel_edp_panel_on()
428 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_panel_on()
444 	u32 pp, idle_off_mask = PP_ON ;  in cdv_intel_edp_panel_off()  local
449 	pp = REG_READ(PP_CONTROL);  in cdv_intel_edp_panel_off()
451 	if ((pp & POWER_TARGET_ON) == 0)   in cdv_intel_edp_panel_off()
455 	pp &= ~PANEL_UNLOCK_MASK;  in cdv_intel_edp_panel_off()
458 	pp &= ~POWER_TARGET_ON;  in cdv_intel_edp_panel_off()
459 	pp &= ~EDP_FORCE_VDD;  in cdv_intel_edp_panel_off()
460 	pp &= ~EDP_BLC_ENABLE;  in cdv_intel_edp_panel_off()
461 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_panel_off()
476 	u32 pp;  in cdv_intel_edp_backlight_on()  local
486 	pp = REG_READ(PP_CONTROL);  in cdv_intel_edp_backlight_on()
488 	pp |= EDP_BLC_ENABLE;  in cdv_intel_edp_backlight_on()
489 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_backlight_on()
497 	u32 pp;  in cdv_intel_edp_backlight_off()  local
502 	pp = REG_READ(PP_CONTROL);  in cdv_intel_edp_backlight_off()
504 	pp &= ~EDP_BLC_ENABLE;  in cdv_intel_edp_backlight_off()
505 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_backlight_off()