115 static void ttc_set_interval(struct ttc_timer *timer,  in ttc_set_interval()  argument
121 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
123 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
125 	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);  in ttc_set_interval()
133 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
147 	struct ttc_timer *timer = &ttce->ttc;  in ttc_clock_event_interrupt()  local
150 	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);  in ttc_clock_event_interrupt()
164 	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;  in __ttc_clocksource_read()  local
166 	return (cycle_t)readl_relaxed(timer->base_addr +  in __ttc_clocksource_read()
187 	struct ttc_timer *timer = &ttce->ttc;  in ttc_set_next_event()  local
189 	ttc_set_interval(timer, cycles);  in ttc_set_next_event()
203 	struct ttc_timer *timer = &ttce->ttc;  in ttc_set_mode()  local
208 		ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq,  in ttc_set_mode()
214 		ctrl_reg = readl_relaxed(timer->base_addr +  in ttc_set_mode()
218 				timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_mode()
221 		ctrl_reg = readl_relaxed(timer->base_addr +  in ttc_set_mode()
225 				timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_mode()
465 static void __init ttc_timer_init(struct device_node *timer)  in ttc_timer_init()  argument
484 	timer_baseaddr = of_iomap(timer, 0);  in ttc_timer_init()
490 	irq = irq_of_parse_and_map(timer, 1);  in ttc_timer_init()
496 	of_property_read_u32(timer, "timer-width", &timer_width);  in ttc_timer_init()
500 	clk_cs = of_clk_get(timer, clksel);  in ttc_timer_init()
508 	clk_ce = of_clk_get(timer, clksel);  in ttc_timer_init()
517 	pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);  in ttc_timer_init()