80 	void __iomem *base_addr;  member
121 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
123 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
125 	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);  in ttc_set_interval()
133 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
150 	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);  in ttc_clock_event_interrupt()
166 	return (cycle_t)readl_relaxed(timer->base_addr +  in __ttc_clocksource_read()
214 		ctrl_reg = readl_relaxed(timer->base_addr +  in ttc_set_mode()
218 				timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_mode()
221 		ctrl_reg = readl_relaxed(timer->base_addr +  in ttc_set_mode()
225 				timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_mode()
269 			readl_relaxed(ttccs->ttc.base_addr +  in ttc_rate_change_clocksource_cb()
295 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
305 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
315 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
351 	ttccs->ttc.base_addr = base;  in ttc_setup_clocksource()
363 	writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);  in ttc_setup_clocksource()
365 		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_setup_clocksource()
367 		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_setup_clocksource()
429 	ttcce->ttc.base_addr = base;  in ttc_setup_clockevent()
443 	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_setup_clockevent()
445 		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_setup_clockevent()
446 	writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);  in ttc_setup_clockevent()