Lines Matching refs:clkrst3_base
17 void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, in u8500_clk_init() argument
325 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, in u8500_clk_init()
330 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, in u8500_clk_init()
334 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base, in u8500_clk_init()
338 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base, in u8500_clk_init()
342 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base, in u8500_clk_init()
346 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base, in u8500_clk_init()
351 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base, in u8500_clk_init()
355 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base, in u8500_clk_init()
359 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base, in u8500_clk_init()
493 clkrst3_base, BIT(1), CLK_SET_RATE_GATE); in u8500_clk_init()
497 clkrst3_base, BIT(2), CLK_SET_RATE_GATE); in u8500_clk_init()
501 clkrst3_base, BIT(3), CLK_SET_RATE_GATE); in u8500_clk_init()
505 clkrst3_base, BIT(4), CLK_SET_RATE_GATE); in u8500_clk_init()
509 clkrst3_base, BIT(5), CLK_SET_RATE_GATE); in u8500_clk_init()
514 clkrst3_base, BIT(6), CLK_SET_RATE_GATE); in u8500_clk_init()
518 clkrst3_base, BIT(7), CLK_SET_RATE_GATE); in u8500_clk_init()