101 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8500_clk_init()
109 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8500_clk_init()
112 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8500_clk_init()
115 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8500_clk_init()
150 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8500_clk_init()
169 					CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8500_clk_init()
173 				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);  in u8500_clk_init()
179 				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);  in u8500_clk_init()
184 				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);  in u8500_clk_init()
189 				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);  in u8500_clk_init()
194 				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);  in u8500_clk_init()
199 				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);  in u8500_clk_init()
419 			clkrst1_base, BIT(0), CLK_SET_RATE_GATE);  in u8500_clk_init()
423 			clkrst1_base, BIT(1), CLK_SET_RATE_GATE);  in u8500_clk_init()
427 			clkrst1_base, BIT(2), CLK_SET_RATE_GATE);  in u8500_clk_init()
431 			clkrst1_base, BIT(3), CLK_SET_RATE_GATE);  in u8500_clk_init()
436 			clkrst1_base, BIT(4), CLK_SET_RATE_GATE);  in u8500_clk_init()
441 			clkrst1_base, BIT(5), CLK_SET_RATE_GATE);  in u8500_clk_init()
445 			clkrst1_base, BIT(6), CLK_SET_RATE_GATE);  in u8500_clk_init()
449 			clkrst1_base, BIT(8), CLK_SET_RATE_GATE);  in u8500_clk_init()
453 			clkrst1_base, BIT(9), CLK_SET_RATE_GATE);  in u8500_clk_init()
457 			clkrst1_base, BIT(10), CLK_SET_RATE_GATE);  in u8500_clk_init()
463 			clkrst2_base, BIT(0), CLK_SET_RATE_GATE);  in u8500_clk_init()
467 			clkrst2_base, BIT(2), CLK_SET_RATE_GATE);  in u8500_clk_init()
471 			clkrst2_base, BIT(3), CLK_SET_RATE_GATE);  in u8500_clk_init()
476 			clkrst2_base, BIT(4), CLK_SET_RATE_GATE);  in u8500_clk_init()
480 			clkrst2_base, BIT(5), CLK_SET_RATE_GATE);  in u8500_clk_init()
486 			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);  in u8500_clk_init()
489 			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);  in u8500_clk_init()
493 			clkrst3_base, BIT(1), CLK_SET_RATE_GATE);  in u8500_clk_init()
497 			clkrst3_base, BIT(2), CLK_SET_RATE_GATE);  in u8500_clk_init()
501 			clkrst3_base, BIT(3), CLK_SET_RATE_GATE);  in u8500_clk_init()
505 			clkrst3_base, BIT(4), CLK_SET_RATE_GATE);  in u8500_clk_init()
509 			clkrst3_base, BIT(5), CLK_SET_RATE_GATE);  in u8500_clk_init()
514 			clkrst3_base, BIT(6), CLK_SET_RATE_GATE);  in u8500_clk_init()
518 			clkrst3_base, BIT(7), CLK_SET_RATE_GATE);  in u8500_clk_init()
523 			clkrst6_base, BIT(0), CLK_SET_RATE_GATE);  in u8500_clk_init()