Lines Matching refs:src_reg
72 u32 src_reg; in socfpga_clk_set_parent() local
75 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); in socfpga_clk_set_parent()
76 src_reg &= ~0x1; in socfpga_clk_set_parent()
77 src_reg |= parent; in socfpga_clk_set_parent()
78 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); in socfpga_clk_set_parent()
80 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); in socfpga_clk_set_parent()
81 src_reg &= ~0x2; in socfpga_clk_set_parent()
82 src_reg |= (parent << 1); in socfpga_clk_set_parent()
83 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); in socfpga_clk_set_parent()
85 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); in socfpga_clk_set_parent()
87 src_reg &= ~0x3; in socfpga_clk_set_parent()
88 src_reg |= parent; in socfpga_clk_set_parent()
91 src_reg &= ~0xC; in socfpga_clk_set_parent()
92 src_reg |= (parent << 2); in socfpga_clk_set_parent()
94 src_reg &= ~0x30; in socfpga_clk_set_parent()
95 src_reg |= (parent << 4); in socfpga_clk_set_parent()
97 writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC); in socfpga_clk_set_parent()