Lines Matching refs:hwclk
44 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) in socfpga_clk_get_parent() argument
49 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { in socfpga_clk_get_parent()
53 if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { in socfpga_clk_get_parent()
59 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) in socfpga_clk_get_parent()
61 if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) || in socfpga_clk_get_parent()
62 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) in socfpga_clk_get_parent()
70 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent) in socfpga_clk_set_parent() argument
74 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { in socfpga_clk_set_parent()
79 } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { in socfpga_clk_set_parent()
86 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) { in socfpga_clk_set_parent()
89 } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) || in socfpga_clk_set_parent()
90 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) { in socfpga_clk_set_parent()
103 static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, in socfpga_clk_recalc_rate() argument
106 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_recalc_rate()
124 static int socfpga_clk_prepare(struct clk_hw *hwclk) in socfpga_clk_prepare() argument
126 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_prepare()